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vhdlveri123
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Registered: ‎04-21-2021

Asynchronous FIFO depth

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Hi,

I need to transfer 32 bit between two clock domains having same frequency, what should be the depth of  FIFO in this case?

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avrumw
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Registered: ‎01-23-2009

But in the FIFO generator IP, there is no option to set the depth to 8, it starts from 512.

Have you selected one of the FIFOs that has "Memory Type" of "Distributed RAM"? The FIFO generator needs memory, and there are several kinds of memory available for it to use - mostly Block RAM and Distributed RAM. The Block RAMs are "larger" blocks of memory, with each block RAM being 18kbit or 36kbit - if you are using these, there is no advantage to using less than 18kb (or 16kb if your width isn't a multiple of 9). Since your width is 32, the 16kb ram would be 512x32, which is the smallest it is offering you. 

Distributed RAMs are much smaller - depending on families (and dual port capabilities) they can be 32x2, or 64x1. While these are much smaller, they are "distributed" everywhere on the die - there a MANY more of them then Block RAMs. If you choose to use these then the FIFO generator will probably offer you a minimum size of 32 (instead of 512).

So, in both cases they will be larger than 8 - but that's fine. If you only need 8 and you generate one that has 32, then you will simply never use the remaining 24 elements - they are wasted, but that doesn't really matter. In the case of the Block RAM, you will end up using only a tiny portion of the Block RAM. If you don't need the Block RAM for anything else, that's also fine. It is a little harder to meet timing with Block RAMs (since they are in discrete places on the die and they are slower than distributed RAMs), but if you can meet timing and you don't need the Block RAM for anything else then go ahead and generate the 512x32 and only use the first 8 entries of it.

Avrum

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dgisselq
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Registered: ‎05-21-2015

If the receiving domain is always reading when data is present, then a FIFO of 8 elements should be sufficient.

avrumw
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Registered: ‎01-23-2009

two clock domains having same frequency

When you say "having the same frequency" do you mean "derived from the same clock source but with different propagation paths (or varying phase)" or do you mean from two different oscillators with the same nominal frequency.

If it is the first, then these clocks are "mesochronous" and you can use a clock domain crossing circuit (CDCC) specifically for mesochronous clock domain crossings. These are simplifications of true asynchronous CDCCs. Take a look a this post on the construction of a mesochronous CDCC. (Which is all a more wordy way of saying "8 elements should be sufficient", as @dgisselq said).

If the clocks derive from different clock sources with the same nominal frequency then the answer is "infinite" - it is impossible to bring all data between these two domains. For this kind of CDCC you will need to be able to drop enough samples to account for the maximum parts-per-million (PPM) difference between the two oscillators and also to tolerate gaps in the data on the receiving side (accounting for the cases where the source clock is within the PPM rating of faster/slower than the destination clock).

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vhdlveri123
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Registered: ‎04-21-2021

Thank you.

But in the FIFO generator IP, there is no option to set the depth to 8, it starts from 512.

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dgisselq
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Registered: ‎05-21-2015

@vhdlveri123 ,

I use my own.

The FIFO generator IP is one of the most overblown designs I've ever examined with over a hundred ports and a hundred parameters.  It's overkill for any problem.

Dan

avrumw
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Registered: ‎01-23-2009

But in the FIFO generator IP, there is no option to set the depth to 8, it starts from 512.

Have you selected one of the FIFOs that has "Memory Type" of "Distributed RAM"? The FIFO generator needs memory, and there are several kinds of memory available for it to use - mostly Block RAM and Distributed RAM. The Block RAMs are "larger" blocks of memory, with each block RAM being 18kbit or 36kbit - if you are using these, there is no advantage to using less than 18kb (or 16kb if your width isn't a multiple of 9). Since your width is 32, the 16kb ram would be 512x32, which is the smallest it is offering you. 

Distributed RAMs are much smaller - depending on families (and dual port capabilities) they can be 32x2, or 64x1. While these are much smaller, they are "distributed" everywhere on the die - there a MANY more of them then Block RAMs. If you choose to use these then the FIFO generator will probably offer you a minimum size of 32 (instead of 512).

So, in both cases they will be larger than 8 - but that's fine. If you only need 8 and you generate one that has 32, then you will simply never use the remaining 24 elements - they are wasted, but that doesn't really matter. In the case of the Block RAM, you will end up using only a tiny portion of the Block RAM. If you don't need the Block RAM for anything else, that's also fine. It is a little harder to meet timing with Block RAMs (since they are in discrete places on the die and they are slower than distributed RAMs), but if you can meet timing and you don't need the Block RAM for anything else then go ahead and generate the 512x32 and only use the first 8 entries of it.

Avrum

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