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Registered: ‎08-16-2018

Asynchronous data recovery

I have some streams of serial data at 250 MHz to receive by an Artix-7. Data is asynchronous. The clock that is sent to the system that produces the data is available to the FPGA but the phase is unknown (and also variable within streams). Most of the techniques I've read are about using oversampling. I could do that at 4x or 8x I guess, but would that increase the power consumption or will create tighter time constraints?

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Registered: ‎05-21-2015

Re: Asynchronous data recovery


Mathematically, the minimum oversampling required is more than 2x, and 3x is the minimal integer oversampling value.  That said, I've only ever seen systems that were 4x oversampled.  While 8x oversampling is not unheard of, it is often overkill.

When doing 4x oversampling, do you need a clock running at 250*4=1GHz?  Yes/no.  The ISERDES will need a clock of at least 500MHz, should you choose to use DDR mode.  You don't need to distribute this clock to the rest of your design.  The 250MHz clock will work fine for that purpose.  You will need to operate on four samples at a time should you choose to use the 250MHz clock as your system clock.  (I might choose 125MHz myself ... it's easier to work with, but it would mean I'd need to operate at eight samples per clock.)

As for recovering the clock from the data, the "ideal" approach (maximizes SNR) would be to run the incoming bit-data through a matched filter, sample-by-sample square it, and look for the sine wave that will result at your data rate.  The maximum of that sine wave should  be the point you want to sample the data at.  That should give you the sampling phase you are looking for.  Once you downselect to the one bit of interest, and likely applied a hard decision (1 or 0), your task should be simplified back to what you are intending.

Because you have the 250MHz clock from the source, the phase should neither wander nor need a tracking loop once determined.  This will simplify your design.