02-07-2019 06:21 PM
I am working on a project with 2 FPGAs. There are 32 pairs of GTH between these 2 FPGAs.Every 2 Quad has a reference clock (156.25MHz) coming from a same clock buffer. I use Aurora 64B66B protocol on these GTH. When I instantiates a single Auroua IP with 8 lanes in a project, the connection works fine, the lane up and channel up goes high. when I instantiates a single Aurora IP with 16 lanes in a project, the connection is not working. The lane up and channel up does not go high. When I use 2 single Aurora IP each with 8 lanes in a project, the connection also does not work. The frequency of tx_clk_out is right. The MMCM's lock is locked, the user_clk is with right frequency. But link reset is toggling.
Does any one use multiple Aurora lanes before?
02-08-2019 02:24 AM
it is possible to use more than 8 lanes.
There can be several reasons for the links not to come up.
Do the transceiver PLL lock?
As you say link_reset is toggling, can you check if the core fails to get into block sync?
Did you try your 32 links with an IBERT design? Was this working for all links in a single design?
02-08-2019 08:31 AM
Thank you for answering.
I tried these 16 lanes using Aurora 64B66B core with eight lanes seperately in single project. They both worked fine. One project contained an Aurora 64B66B core with eight lanes 1-8, other project contained an Aurora 64B66B core with eight lanes 9-16. 1-8 lane had a shared gth reference clock, 9-16 lanes had a shared gth reference clock. These two reference clock comed from the same clock buffer. When I tried to combine these 2 core in a single project, the tx_clk_out frequency of both core were right, the user_clk frequency of both core were also right, the MMCM with tx_clk_out as input were locked. But both link reset were toggling, and both core rx had not received any thing under the loop back mode. I did not check PLL lock, as I assumed the PLL lock was locked when tx_clk_outs were right.
I will do the block sync test and IBERT test as soon as possible.
02-08-2019 09:38 AM
another test to try would be with your combined project.
Put one of the cores in power down from the start. See if the other core is coming up.
If it is coming up, then power up the other core and see what happens.