cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Explorer
Explorer
316 Views
Registered: ‎10-09-2018

Aurora and PCIe merge error- artix7

Hello,

system- Artix7(xc7a100t-2fgg484), ISE 14.7, win10-64 bit

 

I am trying to merge 2 Aurora and PCIe into single gtpe2_common.

Here I am using PCIe gtp common and by default PCIe is using PLL0 to drive it's gtp channel. PLL1 is getting used to drive both of the aurora gtpe2_channel( same freq for both aurora) and gtpe2_common in both of the aurora blocks are commented.

to use both PLL of PCIe gtpe2_common, attributes changes made as below:

                     

 

//---------- Simulation Attributes ------------------------------------- 
                                 .SIM_PLL0REFCLK_SEL (3'b001), // 
                                 .SIM_PLL1REFCLK_SEL (3'b010),

                       //---------- Clock Attributes ------------------------------------------ 
                                .PLL0_CFG (27'h01F024C), // Optimized for IES 
                                .PLL1_CFG (27'h01F03DC),//(27'h01F024C), 

                               .PLL0_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES 
                               .PLL1_FBDIV (5),

 

then I am using output port of resp. PLL to PCIe and Aurora channel.

----

I am getting following error:

 

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component <refclk_ibuf> is placed at site <IBUFDS_GTE2_X0Y3>. The GT
   component
   <pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i> is placed at site
   <GTPE2_COMMON_X0Y1>. The GT is driven by this BUFDS in regular mode and they
   must be placed in the same clock region to be routable because the BUFDS
   connects to the GT on a GTREFCLK pin. Furthermore, depending on the GTREFCLK
   bit used, only some BUFDS sites in the same clock region are routable to it.
   Check usage documents for routability of the device. This placement is
   UNROUTABLE in PAR and therefore, this error condition should be fixed in your
   design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING in order to generate an NCD file. This NCD
   file can then be used in FPGA Editor to debug the problem. A list of all the
   COMP.PINS used in this clock placement rule is listed below. These examples
   can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "refclk_ibuf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i.GTREFCLK0" CLOCK_DEDICATED_ROUTE =
   FALSE; >

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component <aurora2_exdes_inst/IBUFDS_GTE2_CLK1> is placed at site
   <IBUFDS_GTE2_X0Y2>. The GT component
   <pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i> is placed at site
   <GTPE2_COMMON_X0Y1>. The GT is driven by this BUFDS in regular mode and they
   must be placed in the same clock region to be routable because the BUFDS
   connects to the GT on a GTREFCLK pin. Furthermore, depending on the GTREFCLK
   bit used, only some BUFDS sites in the same clock region are routable to it.
   Check usage documents for routability of the device. This placement is
   UNROUTABLE in PAR and therefore, this error condition should be fixed in your
   design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING in order to generate an NCD file. This NCD
   file can then be used in FPGA Editor to debug the problem. A list of all the
   COMP.PINS used in this clock placement rule is listed below. These examples
   can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "aurora2_exdes_inst/IBUFDS_GTE2_CLK1.O" CLOCK_DEDICATED_ROUTE = FALSE;
   >
   < PIN
   "pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i.GTREFCLK1" CLOCK_DEDICATED_ROUTE =
   FALSE; >

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

 

I reversed  loc constraint for clock in this issue as suggestion  but nothing happened.

 

--------------------------------------------------

 

 

The differential clock which comes from top module pass through ibufds_gte2 and then it comes to PLL input. I pass this signal through bufh for both pll as below

 

PCIe:
  refclk_ibuf : IBUFDS_GTE2
     port map(
       O       => sys_clk1,
       ODIV2   => open,
       I       => sys_clk_p,
       IB      => sys_clk_n,
       CEB     => '0');

bufg_inst :  bufh
      port map (
           I     => sys_clk1,
           O     => sys_clk
          );
------------------------------------
Aurora:
IBUFDS_GTE2_CLK1 :  IBUFDS_GTE2
      port map (
           I     => GTPQ2_P,
           IB    => GTPQ2_N,
           CEB   => '0',
           O     => GT_REFCLK1,
           ODIV2 => OPEN);
--gtrefclk_aurora <= GT_REFCLK1;

bufg_inst :  bufh
      port map (
           I     => GT_REFCLK1,
           O     => gtrefclk_aurora  -- this signal goes to pll1 input in pcie gtpe2_common
          );

 

 after adding bufh I am getting errors as below:

 

ERROR:Route:471 - 
   This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be
   routed:
Unrouteable Net:pcie_inst/sys_clk
Unrouteable Net:gt_refclk_aurora_s
Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 11 secs 

 

 

In my utilization summary, i noticed this:

 

Number of IBUFDS_GTE2s:                        2 out of       4   50%
    Number of LOCed IBUFDS_GTE2s:                1 out of       2   50%

 

So if i am using 2 IBUFDS then it should show 2 out of 2.

 

--------------------------------###########################

My questions are below:

1) what is the right technique to use both PLL in single quad gtpe2_common.( As I have made changes in attributes only)?

2) If I am using both IBUFDS then why it is showing 1 out of 2(do I need to do anything else to activate 2nd IBUFDS)?

3) what is the correct way to merge different IP into single gtpe2_common(here 2 Aurora & 1 PCIe)?

4) do I need to change any placement constarints in ucf file?

 

I have attached my ucf,ncs,pcf file down below. Please give a look and let me know if you got something for me.

 

Thanks!

Avinash

 

Tags (2)
0 Kudos
Reply
4 Replies
Xilinx Employee
Xilinx Employee
286 Views
Registered: ‎10-19-2011

Hi @avinashc,

please connect the IBUFDS_GTE/O port directly to the COMMON block inputs. A BUFH/BUFG connection would only be needed if you need this clock in fabric. Please check with UG482, page 24, table 2-1.

Check with figure A-4 in UG482 the location constraints for your refclk inputs. Seems you only gave location constraints (or correct ones) to one of them.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Explorer
Explorer
279 Views
Registered: ‎10-09-2018

Hello @eschidl ,

I think i have given proper constraint to both clk and pin.

I have attached some pic, please let me know if you think that is right.

 

--what is the right way to use both IBUFDS_GTE2,as in my code only 1 is getting used out of 2 as i mentioned above.?

-- Can I use both pll0 and pll1 at same time with two different frequency for Aurora and PCIe? ( I have changed attributes for pll1 as I need)

Thanks!

Avinash

pc.jpg
ac.jpg
a4.jpg
0 Kudos
Reply
Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎10-19-2011

Hi @avinashc,

your settings look correct to me except for one point. You give for the Aurora core location constraints for the TX/RX pins and for the channel primitive. Please do not use the two together. One of them is sufficient.

You can use PLL0 and PLL1 completely independent of each other.

If you instantiate two refclk input buffers in the code and connect/constrain them correctly to the different PLLs, I would expect them both to be shown as used.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Explorer
Explorer
256 Views
Registered: ‎10-09-2018


Hello @eschidl ,

Thank you for quick reply.

 

@eschidl wrote:

If you instantiate two refclk input buffers in the code and connect/constrain them correctly to the different PLLs, I would expect them both to be shown as used.


You mean IBUFDS_GTE2, right? (which I have already done).

 

I have commented gtpe2_channel  LOC constraint, still I am getting below errors:

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component <pcie_inst/refclk_ibuf> is placed at site <IBUFDS_GTE2_X0Y3>. The
   GT component
   <pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i> is placed at site
   <GTPE2_COMMON_X0Y1>. The GT is driven by this BUFDS in regular mode and they
   must be placed in the same clock region to be routable because the BUFDS
   connects to the GT on a GTREFCLK pin. Furthermore, depending on the GTREFCLK
   bit used, only some BUFDS sites in the same clock region are routable to it.
   Check usage documents for routability of the device. This placement is
   UNROUTABLE in PAR and therefore, this error condition should be fixed in your
   design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING in order to generate an NCD file. This NCD
   file can then be used in FPGA Editor to debug the problem. A list of all the
   COMP.PINS used in this clock placement rule is listed below. These examples
   can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "pcie_inst/refclk_ibuf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i.GTREFCLK0" CLOCK_DEDICATED_ROUTE =
   FALSE; >

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component <aurora1_exdes_inst/IBUFDS_GTE2_CLK1> is placed at site
   <IBUFDS_GTE2_X0Y2>. The GT component
   <pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i> is placed at site
   <GTPE2_COMMON_X0Y1>. The GT is driven by this BUFDS in regular mode and they
   must be placed in the same clock region to be routable because the BUFDS
   connects to the GT on a GTREFCLK pin. Furthermore, depending on the GTREFCLK
   bit used, only some BUFDS sites in the same clock region are routable to it.
   Check usage documents for routability of the device. This placement is
   UNROUTABLE in PAR and therefore, this error condition should be fixed in your
   design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING in order to generate an NCD file. This NCD
   file can then be used in FPGA Editor to debug the problem. A list of all the
   COMP.PINS used in this clock placement rule is listed below. These examples
   can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "aurora1_exdes_inst/IBUFDS_GTE2_CLK1.O" CLOCK_DEDICATED_ROUTE = FALSE;
   >
   < PIN
   "pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i.GTREFCLK1" CLOCK_DEDICATED_ROUTE =
   FALSE; >

Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:1d47bbe2) REAL time: 28 secs 

Total REAL time to Placer completion: 28 secs 
Total CPU  time to Placer completion: 28 secs 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

 

Thanks!

Avinash

0 Kudos
Reply