10-08-2019 01:46 AM
i am working on a pcb design that includes 2 kintex 7 fpga, in this design, i am using two lanes for auro comm between fpgas. Fpga1 mgt refclk is sourced from a clk oscilator 125 MHz, for fpga2 refclk, i don't use an oscilator, i share refclk of fpga1 from a port of bank16 of fpga1 as a lvds signal and connected to mgt refclk input of fpga2; is this design is ok, could i share refclk between fpgas? İs there a rule for this? Could you help me ? Thanks
10-08-2019 01:57 AM
If I understan dright, you have one 125 Mhz clock driving two clock inputs to the FPGA
Its OK to drive the ref clocks with anything, provided it meets the specifications.
The key one is going to be phase noise and signal distortion.
In particular, the termination is going to have to be spot on.
Is there any reason you dont want to use seperate oscilators ?
10-08-2019 01:59 AM
re reading the question agina,
are you trying to drive the second MGT ref clock with an output of the FPGA ?
If so, I doubt very much that you will meet the phase noise constraints of the MGT clk input.
10-08-2019 02:22 AM
Yes, in my circuit one oscilator and 2 fpgas, fpga1 refclk is sourced from oscilator and fpga2 refclk is from fpga1 out port; is there a doc that tells the limits of phase noise and signal distortion; why do i need two oscilators for this, is not one oscilator enough for this?
10-08-2019 03:54 AM
This is probably the most concise note on phase noise of the MGT clock
from that you need -123 dBc phase noise at 10 KHz,
Thjats very stringent, not all oscilators will do that,
You are not going to get that from any FPGA output,
Why not two clocks ?
oscilators are dead cheap, and by far and away its easiset to route.
Othe rprobelms with one FPGA driving the second FPGA's clock input,
how does second FPGA get a clock before FPGA 1 is configured ?
10-08-2019 04:22 AM
First, your question is not about aurora, but about sourcing clocks.
Being oscillators cheap, small and reliable, I don't understand why skimming a few p on that with two kintex-7... anyways...
Technically, I can't see any problem. If one FPGA can produce the clock you need, that's it. A clock is a clock, whatever the source. You only need to take care of two things:
- Routing and termination: use differential routing technique with a matching impedance and provide the necessary termination. For LVDS it could need capacitive coupling. Use simulation (hyperlynx, etc) to check your clock is good in terms of distortion.
- Jitter: For high frequencies (10G, etc.) reference clock jitter has an impact. Check if that is your case and research whether your FPGA generated clock is good enough.
10-08-2019 08:56 AM
A clock from an FPGA is generally not clean enough to qualify as a reference clock. It would pick up noise from the Vccint domain which would get worse as you add logic to the design. So you could start out with it working and then have it fail when you get your full design loaded.
You would need to send it through a jitter cleaner chip, I believe silabs provide some of these.
Would it be possible to use a clock distribution chip to make multiple copies of the main oscillator output?
10-08-2019 07:35 PM
in your clocking, you have some risk. the clock generated from the FPGA output ports could be noisy and the noise is not deterministic. it depends on the fabric logic design.
also you have a benifit with this clocking. i.e. the clocking is fully synchronous. but Aurora can support +/- 100 ppm asynchronous clocking. you don't have to use a synchronous clocking.
The suggestion is to following the clocking in Figure 1 of xapp1192.
10-14-2019 05:13 AM
Because of noise distortion risk, i have decided to use two osilators for 2 fpgas mgt clks; for fpga1 i will use 1 sfpda 5 Gb, 1 ethernet 1 Gb and 2 lane 5Gb aurora; and for fpga 2, 2 lane 5 Gb aurora; my question is that in fpga 1 i will have one 125 MHz mgt clk; could i implement these 3 comm ( ethernet, aurora 2 lane and 1 sfpda 1 lane), could they work with one mgt clk; my fpga is xc7k160t-1fbg676i, mgt clk is on bank 115 clk0
10-14-2019 07:51 AM
10-14-2019 10:53 PM
Yes i use 125 Mhz for all IPs, and i will share mgt clk by using IP shared logic in core, by using this, i can use IP gtrefclk-out for other IPs; is it ok? Does it works properly? İn my fpga there are 2 mgt quads, is it importat where i connect the mgt clk (refclk0,1-115 or refclk0,1-116) ?
10-14-2019 10:54 PM
I haven't tried it yet, but as you can see in GT transceiver wizard you can set multiple GT to one ref clk, but in your design, this condition relies on your transceivers rate. if you have a different line rate and you want to use one ref Clk, it sounds strange.
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10-14-2019 11:15 PM
in kintex-7, the reference clock can drive the quad itself and one quad above and one quad below.
if there are two adjacent quads are used, it don't matter which clock (refclk0,1-115 or refclk0,1-116) you pick up.