cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
ldkazuma
Observer
Observer
705 Views
Registered: ‎11-11-2019

Boosting GTH transceiver clock input

Jump to solution

I am currently using a 100Mhz offboard reference clock for a 9.6Ghz and 10.4Ghz application. Currently using Zynq Ultrascale+ FPGA.

I've looked at the equations presented in Equation 2-3 and 2-4 in UG576. This is showing me that even if maximize N (to 160) and minimize M (to 1), I'm still only going up to an 8Ghz PLLClkout for a reference input clock of 100Mhz. And I can't set my PLLClkout any lower than 8Ghz because of the nominal frequency ranges in Table 2-12. 

I was considering sending my 100Mhz clock into an MMCM and turning it into a 200Mhz clock before feeding it into the GTH Transceiver, but I'm not sure if this is a viable option. I'm also unsure what the global clocking resources would look like at that point. Not sure if there is a single-ended version of IBUFDS_GTE4. 

Does anyone have any good ideas here?

0 Kudos
1 Solution

Accepted Solutions
borisq
Xilinx Employee
Xilinx Employee
624 Views
Registered: ‎08-07-2007

hi @ldkazuma 

 

I believe the line rate is 9.6Gbps and 10.4Gbps, right?

If so, just select the line rate and select 100Mhz refenrece clock. Please see the figure below.

Vivado will take care of the details in the background.

The reference clock has to be differential. MMCM cannot generate reference clock for GTs as it is noisy and link margin is limited.

 

Thanks,

Boris

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

gth_refclk.png
3 Replies
borisq
Xilinx Employee
Xilinx Employee
625 Views
Registered: ‎08-07-2007

hi @ldkazuma 

 

I believe the line rate is 9.6Gbps and 10.4Gbps, right?

If so, just select the line rate and select 100Mhz refenrece clock. Please see the figure below.

Vivado will take care of the details in the background.

The reference clock has to be differential. MMCM cannot generate reference clock for GTs as it is noisy and link margin is limited.

 

Thanks,

Boris

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

gth_refclk.png
karnanl
Xilinx Employee
Xilinx Employee
614 Views
Registered: ‎03-30-2016

Hello @ldkazuma 

I agree with Boris answer. @borisq 
BTW, What is the problem you want to share with us, I do not understand.

>I've looked at the equations presented in Equation 2-3 and 2-4 in UG576.
>This is showing me that even if maximize N (to 160) and minimize M (to 1),
>I'm still only going up to an 8Ghz PLLClkout for a reference input clock of 100Mhz.

With PLLClkout = 8GHz, you can achieve LineRate=16Gbps.


>And I can't set my PLLClkout any lower than 8Ghz because of the nominal frequency ranges in Table 2-12.

The value in this table is correct. You cannot operate QPLL lower than 8GHz.
But please notice that we can set the divider value (D) to achive lower line-rate.
( So if D=4, Line-rate is 2Gbps, if D=8 Line-rate is 1Gbps and so on ... )

>I was considering sending my 100Mhz clock into an MMCM and turning it into a 200Mhz clock before
>feeding it into the GTH Transceiver, but I'm not sure if this is a viable option.
>I'm also unsure what the global clocking resources would look like at that point. Not sure if there is a single-ended version of IBUFDS_GTE4.

As mentioned by Boris, this is not supported, and it will not work on HW.


You can use 100MHz REFCLK for 28Gbps line-rate, no need to use MMCM. See below.
BORIS_GTY.png


Thanks & regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------
ldkazuma
Observer
Observer
584 Views
Registered: ‎11-11-2019

I wasn't aware there was a transceiver wizard until I dug deeper into the documentation. Thank you very much for the explanation everyone.

0 Kudos