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Visitor
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Registered: ‎08-15-2017

Build time tranceiver tx setting

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Design has GTY that is part of an Ethernet core (include GT subcore in core option selected). Also, 'Enable GT Addtional GT Control/Status and DRP ports, is checked. Using IBERT tool, have been able to run sweeps although not sure if loopback is really working. UltraScale+ device with 25G TRX.

Question:

1. What is currently setting the default TX pre-emphasis settings?

2. If a sweep reveals better TX settings, how do I apply time at build time?The pre-post cursor settings port are available through the GT debug optional port, can i just tie these to constants?

Thanks

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Moderator
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Registered: ‎07-30-2007
 

I believe you have to have the GT in the example design to access this port.  If you find the port in the top level in the debug optional ports you can indeed just set a constant.  The default is 5'h00. For preemphasis it would be txpostcursor_in.  Not all ethernet IP has this in the debug ports if it is not you can follow these directions.  The illustration is for precursor. 

 

With the gt in the example design what you want to do is go down into the hierarchy to the gt and open the gt wizard.  Then on the structural options tab go to all ports and search for txpre and click the txprecursor_in checkbox.  Then regenerate the gt design.

Then as shown in the hierarchy go to the i_ethernet_0_gt_wrapper file and edit the  l_ethernet_0_gt_0 instantiation to add the txprecursor_in port as shown.  You will then have the chore of wiring the signal all the way to the top of the example design. 

 

   .rxpolarity_in(rxpolarity_in_core_0),

   .rxprbscntreset_in(rxprbscntreset_in_core_0),

   .rxprbserr_out(rxprbserr_out_core_0),

   .rxprbssel_in(rxprbssel_in_core_0),

   .txprecursor_in(5'h13),




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txpre.JPG
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Highlighted
Moderator
Moderator
358 Views
Registered: ‎07-30-2007
 

I believe you have to have the GT in the example design to access this port.  If you find the port in the top level in the debug optional ports you can indeed just set a constant.  The default is 5'h00. For preemphasis it would be txpostcursor_in.  Not all ethernet IP has this in the debug ports if it is not you can follow these directions.  The illustration is for precursor. 

 

With the gt in the example design what you want to do is go down into the hierarchy to the gt and open the gt wizard.  Then on the structural options tab go to all ports and search for txpre and click the txprecursor_in checkbox.  Then regenerate the gt design.

Then as shown in the hierarchy go to the i_ethernet_0_gt_wrapper file and edit the  l_ethernet_0_gt_0 instantiation to add the txprecursor_in port as shown.  You will then have the chore of wiring the signal all the way to the top of the example design. 

 

   .rxpolarity_in(rxpolarity_in_core_0),

   .rxprbscntreset_in(rxprbscntreset_in_core_0),

   .rxprbserr_out(rxprbserr_out_core_0),

   .rxprbssel_in(rxprbssel_in_core_0),

   .txprecursor_in(5'h13),




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------


View solution in original post

txpre.JPG
Highlighted
Visitor
Visitor
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Registered: ‎08-15-2017
Thanks for the guidance!
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