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Observer justinhk
Observer
287 Views
Registered: ‎04-03-2019

CDR of Virtex Ultrascale GTY

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What's the recommended CDR setting for PCIE gen2  on GTY (5Gb/s, +/-600ppm offset, -5000ppm to 0ppm SSC)?

I don't find preset setting in IP Wizard...

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Xilinx Employee
Xilinx Employee
213 Views
Registered: ‎08-07-2007

回复: CDR of Virtex Ultrascale GTY

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hi @justinhk 

 

pls check pg156 Clocking section.

https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf

the supported case is 

+/-300 ppm (totally 600 ppm) + no_SSC

or

0 ppm + SSC

Below is the document.

Clocking

The UltraScale Devices Gen3 Integrated Block for PCIe core can be configured to use 100 MHz, 125 MHz, or 250 MHz reference clock. The following applies:

•The reference clock can be synchronous or asynchronous with up to ±300 PPM or 600 PPM worst case. (If spread spectrum clock (SSC) is enabled, the link must be synchronous.)

...

 

Thanks,

Boris

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8 Replies
Xilinx Employee
Xilinx Employee
277 Views
Registered: ‎03-30-2016

Re: CDR of Virtex Ultrascale GTY

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Hello @justinhk 

We do not recommend to use GTY standalone for PCIe protocol, this is why PCIe preset is not available in GTY GUI.
Please use PCIe GUI from Vivado to generate the PCIe IP ( with GTY inside the IP)

- If you are using Xilinx PCIe Hard-block please use (Ultrascale+ PCI Express Integrated Block 1.3) GUI,
  Please use PCIe GUI to generate PCIe IP with Gen2 configuration, and GTY will be generated with default/recommended CDR setting for Gen2.
- If you are using GTY as a PHY with 3rd party Link/Transcaction layer IP, Please generate GTY using (PCIe PHY IP) GUI.

Thanks & regards
Leo

Observer justinhk
Observer
260 Views
Registered: ‎04-03-2019

Re: CDR of Virtex Ultrascale GTY

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I'm using GTY as a PHY (use PMA block).  I'm verifying my own PCS implemented in fabric logic.  What's the recommended way to generate the GTY IP?

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Xilinx Employee
Xilinx Employee
254 Views
Registered: ‎03-30-2016

Re: CDR of Virtex Ultrascale GTY

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Hello @justinhk 


PCI Express PHY is a good place to start.
https://www.xilinx.com/support/documentation/ip_documentation/pcie_phy/v1_0/pg239-pcie-phy.pdf

Please read chapter 1 to check if your device is supported or not.

Hope this helps.

Regards
Leo

Observer justinhk
Observer
239 Views
Registered: ‎04-03-2019

Re: CDR of Virtex Ultrascale GTY

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" While some UltraScale devices contain GTYs, this IP does not support GTY in the UltraScale family"

This is so frustrating.  I'm using VCU108 EVK.  Even though the products claimed the phy support PCIe gen2, it seems there is no way to configure the CDR for PCIE gen2  on GTY (5Gb/s, +/-600ppm offset, -5000ppm to 0ppm SSC).......

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Xilinx Employee
Xilinx Employee
215 Views
Registered: ‎03-30-2016

Re: CDR of Virtex Ultrascale GTY

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@deepeshm, @borisq 
Do you have any input on this ?


Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
214 Views
Registered: ‎08-07-2007

回复: CDR of Virtex Ultrascale GTY

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hi @justinhk 

 

pls check pg156 Clocking section.

https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf

the supported case is 

+/-300 ppm (totally 600 ppm) + no_SSC

or

0 ppm + SSC

Below is the document.

Clocking

The UltraScale Devices Gen3 Integrated Block for PCIe core can be configured to use 100 MHz, 125 MHz, or 250 MHz reference clock. The following applies:

•The reference clock can be synchronous or asynchronous with up to ±300 PPM or 600 PPM worst case. (If spread spectrum clock (SSC) is enabled, the link must be synchronous.)

...

 

Thanks,

Boris

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Observer justinhk
Observer
159 Views
Registered: ‎04-03-2019

回复: CDR of Virtex Ultrascale GTY

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Hi @borisq @karnanl 

Because preset is not availiable in GT wizard and the PCIe PHY Logicore also not support Ultrascale GTY.  So, how to set the GTY CDR in GT wizard or DRP to supppot PCIe Gen2 electrical signal?

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Xilinx Employee
Xilinx Employee
135 Views
Registered: ‎08-07-2007

回复: CDR of Virtex Ultrascale GTY

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hi @justinhk 

 

if think you can generate PCIe Integrated Block IP for Ultrascale GTY, can copy the GTY wrappers to your project.

Here is an example reference for 7 series.

https://www.xilinx.com/support/answers/62530.html

 

Thanks,

Boris

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