05-15-2018 08:53 AM
I have Virtex 7 Transceiver Quad connected to two different sources:
2 channels connected to one silicon and 2 other channels to another silicon.
In this setup only one pair locks on data, and the other is failing.
Is it a known limitation? Or is it a matter of configuration?
If I use separate Quad to connect with second silicon, but the reference clock is the same, will it work?
05-15-2018 10:05 AM
This is not a limitation, but probably a configuration problem. What are the data rates you are trying to capture for each of the sources? are they different by more than 1000 ppm? You may need to have a separate reference clock for each data source you are trying to capture.
05-29-2018 01:28 AM
I believe your looking to know are there any limitation on configuration which your using .
there are no limitation , can you let us know what is clocking structure your using and also the what is issue your facing on the board .
05-29-2018 05:15 AM
Refclock is fed through QPLL (GTXE_COMMON) and fed to all 4 channels.
Recovered RX clock from channel 0 is used via PLL as RXUSRCLK. RX buffer is enabled and the clock source is RXCLKOUT.
Two channels are connected to one external source, and lock well. Two other channels are connected to another source and can't lock.
06-13-2018 11:15 AM - edited 06-13-2018 11:37 AM
You need to look at the frequency of the input and the output of the clocks driving the RX buffers. When the RXUSRCLK is derived from a different source than what is driving the RX inputs for the channel it will cause the RX buffer to overflow or underflow. If you are driving inputs into the quad that are based on different reference clocks on the far end you will need to either use 2 different RXUSRCLKs, derived from the inputs (RXOUTCLK) of each of the far end silicon devices, or use a protocol that has clock correction.
06-13-2018 08:07 PM
are Virtex-7, Silicon 1 and Silicon 2 sharing the same clock source oscillator?