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Visitor markus_iis
Visitor
1,924 Views
Registered: ‎11-26-2015

Change QPLL Linerate GTH (QPLL)

Hello,

We have a Zynq Ultrascale+ device and we want to change the linerate of the GTH-Transceiver dynamically (4, 6, 8, 10 and 12 Gbit).

We tried to reconfigure the QPLL1 (Common) and the Transceiver via DRP and apply a reset afterwards. The configuration settings were extracted from GT-Wizard designs that where configured for the wanted linrate and that work on the hardware.

The problem is that the QPLL1 does not lock after the reconfiguration.

We tried to simulate the change of the linerate, but here the QPLL1 locks independent from the reference clock. But this seems to be a normal behaviour: https://www.xilinx.com/support/answers/71190.html.

Interestingly the QPLL1 does not lock in simulation after the linerate change via DRP. We are debugging this behaviour at the moment.

Does the dynamic change of the QPLL1 linrate work for Ultrascale+ Devices?

 

Best regards,

Markus

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13 Replies
Moderator
Moderator
1,865 Views
Registered: ‎07-30-2007

Re: Change QPLL Linerate GTH (QPLL)

It should work.  I'm not sure of what attributes your are changing with the DRP.  Normally you create a GT wizard designs with the intended line rates and compare parameters.  For some designs there might be no attributes changes and you would only change the T/RXOUT_DIV settings.  If you have to change attributes over the DRP you must do a full reset of the qpll and gt when you are done.  Be careful in a loopback scenario you must have a stable RX input during the RX reset otherwise the clock data recovery could lock to the wrong frequency.




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Visitor markus_iis
Visitor
1,834 Views
Registered: ‎11-26-2015

Re: Change QPLL Linerate GTH (QPLL)

thank you for your answer Roy.

we got the attributes that we change via DRP exactly how you described. But we are cross-checking the attributes at the moment to verify that we did not miss something.

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Observer manojmanghwani
Observer
1,808 Views
Registered: ‎05-30-2018

Re: Change QPLL Linerate GTH (QPLL)

Hi,
I have been trying the same experiment as @markus_iis, to reconfigure GTH-TX data-rate using
DRP_COMMON on Kintex Ultrascale XCKU060 part number.

Step#1: At power-up GTH are running @ 8Gbps. QPLL1 lock is good. Refclk to GTH = 200MHz
GTHE3_common is part of the "core" itself. Oscilloscope shows GTH-TX is running @ data-rate (8Gbps).
So far, it
 is all good!

Step#2: Using DRP-COMMON interface: readback  QPLL1_FBDIV_N (@ drp addr = 9'h094) is 0x28.
             So far, this is looking good.
Step#3:Using DRP-COMMON interface: configure QPLL1_FBDIV_N (@ drp addr = 9'h094) to 0x3C.
Step#4: Using DRP-COMMON interface: readback  QPLL1_FBDIV_N (@ drp addr = 9'h094) is 0x3C.
             So far, this is looking good.
Step#5: Bring "gtwiz_reset_rx_pll_and_datapath_in" to 1 for 20milli-sec. 
Step#6: Bring "gtwiz_reset_rx_pll_and_datapath_in" to 0.
Step#7: Oscilloscope shows GTH-TX is running @ newer data-rate (12Gbps). So far, this is ok.
Step#8: QPLL1_LOCK which is zero. This is where the problem is!
Step#9: To fix this issue, tried this: gtwiz_reset_tx_datapath_in to 1 for 20milli-sec. Then, 
gtwiz_reset_tx_datapath_in to zero. But, by this time, GTH-TX output would die completely.

Question: Is "gtwiz_reset_rx_pll_and_datapath_in" the right RESET to apply after 
configuration, or should there be some other? 

Thank you.

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Visitor markus_iis
Visitor
1,779 Views
Registered: ‎11-26-2015

Re: Change QPLL Linerate GTH (QPLL)

We have also an update.

We got the Simulation running. Now we can change the linerate there from 4 Gbit to 12 Gbit and back.

The problem was the value that we wrote via DRP to the common register 0098h. At first we wrote 0x0820 to this register (this value was read from the register with chipscope in a working gtwizard-desgin). Then we read the register 0098h from a working gtwizard-design in the simulation it was 0x0840. So we changed this value in our simulation where we reconfigure our QPLL and then it worked. The strange thing is that the bits (5 and 6) that are different in between 0x0820 and 0x0840 are documented nowhere.

Unfortunately it is still not working in the real design.

Regarding the problem of manojmanghwani. We use as reset the gtwiz_reset_all_in-signal from the GT-Wizard (we use vivado2017.4 and the Transceivers Wizare 1.7: https://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_7/pg182-gtwizard-ultrascale.pdf).  We switch this signal manually with a VIO.

 

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Observer manojmanghwani
Observer
1,724 Views
Registered: ‎05-30-2018

Re: Change QPLL Linerate GTH (QPLL)

Hello, 
As per @markus_iis feedback, I experimented the following on HW:

Scenario#1: Power-off/on, reprog. the bitfile.
Perform DRP-configuration (step# 1 to step# 4 remain same as prev. post) : 
Assert and De-assert "gtwiz_reset_all_in" signal (going to the gth core) doesn't help.
The new data-rate doesn't take effect!

Scenario#2: Power-off/on, reprog. the bitfile.
Perform DRP-configuration (step# 1 to step# 4 remain same as prev. post) : 
Assert and De-assert "gtwiz_reset_all_in" signal (going to example_init FSM) this time. It doesn't help either. The new data-rate doesn't take effect!

Summary:
Assert and de-assert of "gtwiz_reset_rx_pll_and_datapath_in" (past DRP reconfig) helps to switch to the new data-rate. However, QPLL1_LOCK never gets asserted afterwards!

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Xilinx Employee
Xilinx Employee
1,635 Views
Registered: ‎11-29-2007

Re: Change QPLL Linerate GTH (QPLL)

hello,

maybe this is trivial, but please when doing DRP write operations, always do read, modify, write.

Some DRP registers are used to describe multiple attributes and a very common issue is that the wrong attribute is modified by mistake.

 

As Roy said, if the same port and attribute configuration is reproduced, there is no reason for the GT to fail.

I have two caveats in mind:

  • the design has been generated for a lower speed and when we increase the rate of the GT and in turn this increases the frequency of TX/RXUSRCLK, the timing fails in the fabric. So in case of multiple rate design it is always good to constrain the fabric for highest speed.
  • in case of presence of CPLL calibration circuit, if we modify the datarate also the calibration circuit should be updated. Please refer to https://www.xilinx.com/support/answers/70485.html

Hope it helps

GG

 

 

Observer manojmanghwani
Observer
1,606 Views
Registered: ‎05-30-2018

Re: Change QPLL Linerate GTH (QPLL)



Hello @gguasti,
Thank you for owning this ticket.

I believe your suggestions regarding CPLL do not apply here as
we are using QPLL1 on Kintex Ultrascle (GTHE3_common).

Yes, we have been doing RMW and that's how we confirm that the DRP
values we change actually make it through.

Yes, the design has been constrained for faster data-rates.

In case you have not, can you please review @manojmanghwani's inputs from the
following two dates (posted within the same-thread):
a. 11-21-2018 12:18 PM
b. 1‎1-26-2018 10:31 AM

Please also read the question regarding "resets".
We will wait for your feedback.






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Visitor markus_iis
Visitor
1,582 Views
Registered: ‎11-26-2015

Re: Change QPLL Linerate GTH (QPLL)

Hello @gguasti,

 

it´s the same for us.

We also use the QPLL1 but we have a Zynq Ultrascale+ FPGA (GTHE4_COMMON).

We also do RMW and have constraint for the fastest linerate. If we use the GT-Wizard-Designs directly it is working for every linerate.

 

Best regards,

Markus

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Xilinx Employee
Xilinx Employee
1,510 Views
Registered: ‎11-29-2007

Re: Change QPLL Linerate GTH (QPLL)

hello,

please can you assert QPLL0/1RESET directly?

you might refer to pag 61, UG576

is the QPLL0/1LOCK still low after reset?

and if you bring back to original situation all ports and registers, is the QPLLLOCK high after QPLL reset?

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Highlighted
Observer manojmanghwani
Observer
1,466 Views
Registered: ‎05-30-2018

Re: Change QPLL Linerate GTH (QPLL)


Thank you for striving to help us, @gguasti

Please note we could not try both of your experiments as the access to
qpll1reset_in pin is not possible. It has been "greyed" out, Please review
the attachment/screenshot.

qpll1 is our default PLL for GTH core. gtrefclk01_in is the pin on serdes  
module for clock source, 200MHz.  

Kindly let us know if there is any other experiment to be tried.

qpll1reset_in_greyed_out.png
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Xilinx Employee
Xilinx Employee
1,333 Views
Registered: ‎11-29-2007

Re: Change QPLL Linerate GTH (QPLL)

hello, happy new year

yes those ports are disabled but the wizard example design handles the QPLL reset directly.

In the PG182 the reset FSMs are documented:

Image 075.png

You can trigger the QPLL reset by asserting the signal

gtwiz_reset_rx_pll_and_datapath_in

I hope this helps

 

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Observer manojmanghwani
Observer
1,281 Views
Registered: ‎05-30-2018

Re: Change QPLL Linerate GTH (QPLL)

Hello @gguasti,
HNY-2019

With your reply, you have corroborated a part of my question. Thanks!
Please refer my post dated (‎11-21-2018 12:18 PM and shown above that
has the question)
gtwiz_reset_rx_pll_and_datapath_in is indeed the correct RESET one 
should be using.

Coming back to running your experiment:
Anytime I assert and deassert the "gtwiz_reset_rx_pll_and_datapath_in"
flag, esp. after performing the DRP, then
 QPLL1_LOCK goes low and keeps
low forever after that.

Examples:
1. After you change the N (QPLL1_FBDIV_N ) to a new value and
then assert-deassert gtwiz_reset_rx_pll_and_datapath_in, 
QPLL1_LOCK
keeps low 

2. After you re-write the N (QPLL1_FBDIV_N ) with the same value
(as prev. stored value, also, it's the same value as orig. value from gth-
wizard) and then assert-deassert gtwiz_reset_rx_pll_and_datapath_in, 
QPLL1_LOCK 
keeps low 


3. If you simply assert and deassert gtwiz_reset_rx_pll_and_datapath_in"
flag, without performing any DRP or in other words, without touching N
(QPLL1_FBDIV_N ) then, QPLL1_LOCK keeps high (which is good). 

Question:
In addition to steps shown in my
post dated (‎11-21-2018 12:18 PM and shown
above)
, are there any special registers one should program for Line-rate
changes?

Thank you.

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Visitor markus_iis
Visitor
898 Views
Registered: ‎11-26-2015

Re: Change QPLL Linerate GTH (QPLL)

Hello,

 

we found our problem regarding the reconfiguration of the QPLL-Linerate.

We accidentially reconfigured just one of the two QPLLs that we use. So the overall locked-signal was still 0. Now that we reconfigure both it is working. We did not change anything else.

 

Best regards,

Markus

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