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Explorer
Explorer
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Registered: ‎09-06-2019

Changing the Zynq US+ SATA peak to peak voltage

Hi I'm trying to find where I can change the Vpp of SATA 0 on the PS side of a Zynq Ultrascale+ device to maximize the swing on the lane, i.e. 0.85V. Can anyone tell me which registers need to be updated to do so?

Thanks!

EDIT: It looks like the required register (as presented by UG1085) seem like they are missing - can we not write to these?? Looking through the ps init tcl along with the phy linux driver looks like these are never referenced.

Capture.PNG

table.PNG

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Moderator
Moderator
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Registered: ‎07-30-2007

I believe it is possible to set registers during configuration.  At any rate you should be able to read them back and see.  The ones you have circled are the right registers.




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Explorer
Explorer
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Registered: ‎09-06-2019

Hi @roym 

The circled registers in the picture are not the same - they illustrate that registers Lx_TX_ANA_TM_15 and Lx_TX_ANA_TM_16 are not present in UG1087. The first picture shows that the registers I'm interested do not exist in the register map, the second picture shows the registers I'm trying to locate the base address for (the table only provides a memory offset within the register set but does not provide the absolute base address in the system).

The first image on the previous post (from UG1087, https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html) completely skips those register in the map, they are not found when using the provided search function so there is no way to know which address to read/write from/to.

What are the base addresses for registers Lx_TX_ANA_TM_15 and Lx_TX_ANA_TM_16? Or are the memory offsets provided in UG1085 meant to be the offsets from the SERDES absolute register offset? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2008

Hi @badFITimage 

GTR SATA/USB3.0 differential voltage swing is adjusted by Vivado IPI PCW and it is not in users hand. These settings comes from Vivado IPI PCW block and export to the HDF (2019.1 & older Vivado s/w) OR XSA (2019.2 & onward s/w version) to the FSBL. So SATA is certified to support GEN-I/II/III standard with respective rates of 1.5, 3.0, or 6.0 Gb/sec. So user should not touch these settings from GTR perspective. If you find any issues with the SATA GEN-I/II/III interface with correct PCB guidelines specified in UG583, then please let us know and we can have a look what issues you are seeing it with the SATA interface. We have tested some of the SSD over the ZynqMP -> https://www.xilinx.com/support/answers/68663.html. Let us know if you need any help in your custom board to get it working with correct speed and performance for the SATA SSD interface.

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Explorer
Explorer
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Registered: ‎09-06-2019

Hi @jadhavs 

Thanks for the reply - makes sense why this register isn't a part of UG1087. 

Our design utilizes a port multiplier that needs a higher Vpp than what the default configuration offers us. We believe we have some path loss that is attenuates our signal leading to the inability to connect at Gen-III speeds. We would like to increase the Vpp to see if we can't open the eye a little bit more. This may not work but we would like to try it out. Could you help us with this?

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