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Registered: ‎12-30-2019

Changing the data_width of GTH with DRP


I want to change the data width of GT and I have some problem about it. I want to change the data width from 64 bit with TX/RX_INT_datawidth = 1 to 32 bit data width with TX/RX_INT_datawidth = 0. based on the UG576 I know the relationship between TXuserclock and TXuserclock2 will not change and these two condition have the same relationship. I used my own PRBS generator with 64 and 32 bit output width and connect it to TX side. I looped back the data with 001 and see the PRBS of TX side in ILA of RX side. I expect that when I change 64 bit to 32 bit the ILA in RX side show me 32 bit data not 64 bit data. but when I change the width and INT data with DRP, the system behavior does not change. I will be glad if anyone can help me with this problem.

2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-10-2008

Did you reset the GT channel after you run the DRP operation?

Besides, once you plan to modify one parameter, you actually need to generate two xci files, one with the 64-bit interface and another with the 32-bit. You compare the two xci files and find out all the differences between them (some times a few parameters need to be changed, not only the one you care). after that, you use DRP to modify all these parameters, reset the gt channel, and then see if it works.

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Xilinx Employee
Xilinx Employee
Registered: ‎03-30-2016

Hello @ebrahim_nouri 

Do you have any updates on this post ? Is @iguo asnwer enough for you ?
If you find @iguo's answer is useful, could you please kindly marked this thread as Solved , so other users can learn from your experience ?

Thanks & regards

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