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Explorer
Explorer
277 Views
Registered: ‎04-21-2017

Clock spec for 10GEMAC and 12G-SDI IP cores

Dear Forum,

For the 10GEMAC and 12G-SDI IP cores, do Xilinx publish a clock spec for the external clock sources that will be used to drive these cores? 

Regards,

DJE666

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Moderator
Moderator
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Registered: ‎07-30-2007

Re: Clock spec for 10GEMAC and 12G-SDI IP cores

If you're talking about the source for GT reference clocks, they are talked about in the GT user guides and a phase noise spec can be found in data sheet.  Basically it has to be LVDS or LVPECL and meet the phase noise specs.




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Xilinx Employee
Xilinx Employee
216 Views
Registered: ‎03-30-2016

Re: Clock spec for 10GEMAC and 12G-SDI IP cores

Hello @dje666 

Just adding my two cents. Datasheet for your device should cover phase spec requirement for your GT REFCLK.
For example if you are using Kintex US+ GTH then refer to Table 55 for this information.

Regards
Leo

Table55.png
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Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎03-30-2016

Re: Clock spec for 10GEMAC and 12G-SDI IP cores

Hello @dje666 

Do you have any updates on this post ?
If you find @roym 's  answer is useful, could you please kindly marked this thread as Solved , so other users can learn from your experience ?

Thanks & regards
Leo

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