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ttzotzaros
Observer
Observer
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Registered: ‎02-14-2018

Constraining GTY transceiver on Virtex Ultrascale device

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Hello

 

I have designed a 10Gbps PHY which drives an SFP. The design uses a GTY transceiver generated from the wizard, a 64/66b scrambler/descrambler, a block sync state machine and encoder/decoder.

My FPGA is a Virtex Ultrascale XCVU125.

 

When I implement the design, I get the following warning (DRC tab)

 

TIMING #1 Warning The clocks rxoutclk_out[0] and txoutclk_out[0] are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks rxoutclk_out[0]] -to [get_clocks txoutclk_out[0]]

 

How I constraint these clocks? I have read in https://www.xilinx.com/support/answers/64351.html, that for Ultrascale devices, no constraint is needed.

 

Thank you in advance

 

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gguasti
Moderator
Moderator
2,520 Views
Registered: ‎11-29-2007

hello

the RXOUTCLK phase is not known by Vivado, as it is modified by the Phase Interpolator. The message I take from Vivado is that two clock domains with unknown phase relationship are clocking the same logic. You should check what this logic is doing. 

It might be a synchronizer, in this case everything is expected. Otherwise it could be a true error.

hope it helps 

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gguasti
Moderator
Moderator
2,553 Views
Registered: ‎11-29-2007

hello,

if the two clock domains are completely independent (no logic in common) I think you could disregard this warning

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ttzotzaros
Observer
Observer
2,531 Views
Registered: ‎02-14-2018

Thank you for your reply

 

In fact there is a small bit of logic between these two clocks, but it is outside of a GT wrapper.

 

Should I discard this warning?

When I run report_timing I get these:

 

report_timing -from [get_clocks rxoutclk_out[0]] -to [get_clocks txoutclk_out[0]]

.........


Timing Report

Slack (MET) :             4.668ns  (required time - arrival time)
  Source:                 PHY/decoder_64b66b/c7_reg/C
                            (rising edge-triggered cell FDCE clocked by rxoutclk_out[0]  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            probe3_1_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by txoutclk_out[0]  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             txoutclk_out[0]
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.400ns  (txoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns)
  Data Path Delay:        2.354ns  (logic 0.117ns (4.970%)  route 2.237ns (95.030%))
  Logic Levels:           0  
  Clock Path Skew:        0.598ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.003ns = ( 8.403 - 6.400 )
    Source Clock Delay      (SCD):    1.405ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.019ns (routing 0.092ns, distribution 0.927ns)
  Clock Net Delay (Destination): 1.673ns (routing 0.557ns, distribution 1.116ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rxoutclk_out[0] rise edge)
                                                      0.000     0.000 r  
    GTYE3_CHANNEL_X0Y36  GTYE3_CHANNEL                0.000     0.000 r  PHY/gt_transceiver/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye3_top.gtwizard_ultrascale_0_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_channel_container[9].gen_enabled_channel.gtye3_channel_wrapper_inst/channel_inst/gtye3_channel_gen.gen_gtye3_channel_inst[0].GTYE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.071     0.071    PHY/gt_transceiver/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye3_top.gtwizard_ultrascale_0_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/rxoutclk_out[0]
    BUFG_GT_X0Y217       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.386 r  PHY/gt_transceiver/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye3_top.gtwizard_ultrascale_0_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O
    X0Y9 (CLOCK_ROOT)    net (fo=297, routed)         1.019     1.405    PHY/decoder_64b66b/rx_clk
    SLICE_X3Y548         FDCE                                         r  PHY/decoder_64b66b/c7_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y548         FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.117     1.522 r  PHY/decoder_64b66b/c7_reg/Q
                         net (fo=1, routed)           2.237     3.759    xgmii_rxc[7]
    SLICE_X4Y549         FDRE                                         r  probe3_1_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk_out[0] rise edge)
                                                      6.400     6.400 r  
    GTYE3_CHANNEL_X0Y36  GTYE3_CHANNEL                0.000     6.400 r  PHY/gt_transceiver/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye3_top.gtwizard_ultrascale_0_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_channel_container[9].gen_enabled_channel.gtye3_channel_wrapper_inst/channel_inst/gtye3_channel_gen.gen_gtye3_channel_inst[0].GTYE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.047     6.447    PHY/gt_transceiver/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye3_top.gtwizard_ultrascale_0_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_tx_user_clocking_internal.gen_single_instance.gtwiz_userclk_tx_inst/txoutclk_out[0]
    BUFG_GT_X0Y216       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.730 r  PHY/gt_transceiver/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gtye3_top.gtwizard_ultrascale_0_gtwizard_gtye3_inst/gen_gtwizard_gtye3.gen_tx_user_clocking_internal.gen_single_instance.gtwiz_userclk_tx_inst/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O
    X0Y8 (CLOCK_ROOT)    net (fo=589, routed)         1.673     8.403    tx_clk
    SLICE_X4Y549         FDRE                                         r  probe3_1_reg[7]/C
                         clock pessimism              0.000     8.403    
                         clock uncertainty           -0.035     8.368    
    SLICE_X4Y549         FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059     8.427    probe3_1_reg[7]
  -------------------------------------------------------------------
                         required time                          8.427    
                         arrival time                          -3.759    
  -------------------------------------------------------------------
                         slack                                  4.668

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gguasti
Moderator
Moderator
2,521 Views
Registered: ‎11-29-2007

hello

the RXOUTCLK phase is not known by Vivado, as it is modified by the Phase Interpolator. The message I take from Vivado is that two clock domains with unknown phase relationship are clocking the same logic. You should check what this logic is doing. 

It might be a synchronizer, in this case everything is expected. Otherwise it could be a true error.

hope it helps 

View solution in original post

logictable
Adventurer
Adventurer
2,481 Views
Registered: ‎11-13-2017

It looks like you are probing something in the RX datapath with the TX clock. Are you sure this is what you want?

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