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dgoaranda
Newbie
Newbie
407 Views
Registered: ‎05-21-2020

Could I drive GTREFCLK0 port with an PLLE2_BASE output?

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Hi,

In my current project I use a GTP transceiver. I would like to know if I could drive the GTREFCLK0 port of the GTPE2_COMMON module using the output from a PLLE2_BASE.I would use the output of IBUFDS_GTE2 to drive the input of the PLL module and not to drive the GTREFCLK0 port directly because my clock signal has a low frequency and I need to increase the frequency through the PLL to achieve the wanted transmision rate.

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karnanl
Xilinx Employee
Xilinx Employee
371 Views
Registered: ‎03-30-2016

Hello @dgoaranda 

No, this usecase is not possible. You need to use external clock source for GTP reference clock.

Please note that GTP reference clock need to adhere Phase Noise requirement as mentioned by :
https://www.xilinx.com/support/answers/44549.html

Thanks & regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
372 Views
Registered: ‎03-30-2016

Hello @dgoaranda 

No, this usecase is not possible. You need to use external clock source for GTP reference clock.

Please note that GTP reference clock need to adhere Phase Noise requirement as mentioned by :
https://www.xilinx.com/support/answers/44549.html

Thanks & regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

dgoaranda
Newbie
Newbie
336 Views
Registered: ‎05-21-2020
Got it. Thank you very much