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Adventurer
Adventurer
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Registered: ‎01-19-2012

DC coupling an GTX Receiver with a 3.3 V CML Transmitter

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I plan on interfacing a Kintex 7 GTX Transceiver with an external logic chip and have a question about my calculation behind the DC coupling.

My transmitter is a 3.3V CML smart gate (NB7L86M) which has output termination of 50 Ohms to VCC (3.3V). The GTX RX is 50 Ohms terminated to either GND or or VMGTAVTT, which DS182 says is 1.2V. I would like these two chips to be DC coupled.

The common mode of the TX chip is around 3.1 V, so the input current into the FPGA pin would be the current through the 50 ohm input resistor, or (3.1-1.2) / 50  = 38 mV if terminated to VMGTAVTT. According to Table 1 of DS182, the IDCIN-MGTAVTT is 12 mA max, so this chip would not work, correct?

Also, in Table 1 of the DS182, it has Vin (RX and TX absolute input voltage) with a maximum of 1.26 V, so again, this would not work, yes?

Thanks

 

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Xilinx Employee
Xilinx Employee
477 Views
Registered: ‎08-07-2007

hi @kwiatlab 

 

your caculation is correct. that cannot work.

below is guideline for DC coupling.

https://www.xilinx.com/support/documentation/application_notes/xapp1096-dc-coupling-gtx-transceivers.pdf

 

Also you need to take care of the VIN according to Table 54 in DS182.

https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

Thanks,

Boris

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1 Reply
Xilinx Employee
Xilinx Employee
478 Views
Registered: ‎08-07-2007

hi @kwiatlab 

 

your caculation is correct. that cannot work.

below is guideline for DC coupling.

https://www.xilinx.com/support/documentation/application_notes/xapp1096-dc-coupling-gtx-transceivers.pdf

 

Also you need to take care of the VIN according to Table 54 in DS182.

https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

Thanks,

Boris

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