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apogeedbkxilinx
Adventurer
Adventurer
254 Views
Registered: ‎04-02-2010

DRP control of PLL selection in GTHs

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I found this discussion on the forum that states that PLL section (CPLL, QPLL0, QPLL1) is only possible using a port and is not possible using the DRP (dynamic reconfiguration port).

https://forums.xilinx.com/t5/Serial-Transceivers/GTY-Serdes-DRP-Configurations-for-ref-clock-selection/m-p/1064155#M6560

It this also true for the GTHs in the Ultrascale FPGAs?

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kdeshwal
Xilinx Employee
Xilinx Employee
185 Views
Registered: ‎11-12-2019

Hi @apogeedbkxilinx ,

Yes, it is also true for GTH.

We have pair of ports, each for RX & TX exclusively in GTH & GTY both:
     RXSYSCLKSEL[1:0]
     RXPLLCLKSEL[1:0]
     TXSYSCLKSEL[1:0]
     TXPLLCLKSEL[1:0]

Refer UG576(page-42) for details.

Thanks,
Kuldeep

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kdeshwal
Xilinx Employee
Xilinx Employee
186 Views
Registered: ‎11-12-2019

Hi @apogeedbkxilinx ,

Yes, it is also true for GTH.

We have pair of ports, each for RX & TX exclusively in GTH & GTY both:
     RXSYSCLKSEL[1:0]
     RXPLLCLKSEL[1:0]
     TXSYSCLKSEL[1:0]
     TXPLLCLKSEL[1:0]

Refer UG576(page-42) for details.

Thanks,
Kuldeep

-------------------------------------------------------------------------------------------------------------
Please give Kudo and Accept as a Solution if solution provided seems helpful.
Have a look at our Versal Design Process Hub, Versal Blogs and the Versal Forum Useful Resources
-------------------------------------------------------------------------------------------------------------

View solution in original post