03-20-2019 08:58 AM
I have bad quality 10Gbps JESD link between ADC and Kintex US. It has a lot of data errors (BER=10^-6..10^-5) and works when DFE is used only. Scrambler is ON in the JESD configuration. I found optimal TX parameters in the ADC (minimal Swing voltage, no de-emphasis)
I made IBERT and found that errors are absent when standard PRBS(7, 15, 23, 31) are used. Open area is in range 700-2200. Then I add RX PRBS checking to my project (with Xilinx JESD / JESD Phy cores) and found PRBS errors. Investigation shows that some internal GTH parameters in the IBERT core differs from JESD Phy. Ok. I change parameters in the JESD Phy (most of them are undocumented and related with CDR, DFE, AGC). Number of error is decreased significantly; PRBS7-16 are clean. But single errors still present with PRBS 23 and 31 (BER=10^-9). Number of errors in JESD data link is decreased to 10^-9..10^-7 (various values on differ lanes)
Is any ideas
1) Why PRBS results differ in the IBERT and my project and both not correspond to data transmission?
2) How to repair link?
PS There is a list of parameters that was changed:
.GTHE3_CHANNEL_ADAPT_CFG0 (16'hf801), // (16'b1111100000000000),
.GTHE3_CHANNEL_ADAPT_CFG1 (16'h0200), // (16'b0000000000000000),
.GTHE3_CHANNEL_RXCDR_CFG0 (16'h2000), // (16'b0000000000000000),
.GTHE3_CHANNEL_RXCDR_CFG2 (16'h07e6), // (16'b0000011101100110),
.GTHE3_CHANNEL_RXCDR_CFG2_GEN3 (16'h07e6), // (16'b0000011111100110),
.GTHE3_CHANNEL_RXCFOK_CFG1 (16'h0165), // (16'b0000000001100101),
.GTHE3_CHANNEL_RXDFELPM_KL_CFG1 (16'h0002), // (16'b0000000000110010),
.GTHE3_CHANNEL_RX_BIAS_CFG0 (16'h0AB4), // (16'b0000101010110100),
.GTHE3_CHANNEL_RX_DFE_AGC_CFG1 (3'h4), // (3'b000),
.GTHE3_CHANNEL_RX_DFE_KL_LPM_KH_CFG1 (3'h4), // (3'b000),
.GTHE3_CHANNEL_RX_DFE_KL_LPM_KL_CFG1 (3'h4), // (3'b000),
.GTHE3_CHANNEL_RX_SUM_IREF_TUNE (4'h0), // (4'b1100),
.GTHE3_CHANNEL_RX_SUM_RES_CTRL (2'h0), //(2'b11),
.GTHE3_COMMON_QPLL0_CFG4 (16'h0009), // (16'b0000000000000000),
03-22-2019 08:47 AM
if the IBERT shows errors but your design has many errors this can be due to
1) (trivial) we are not using the same RX setup
2) (less trivial) the increased activity in the FPGA due to JESD IP is not supported by a good and well filtered power supply - I would check the power supplies quality
All those listed parameters in your post are reserved and we do not need to set them.
I would rather generate again the JESD PHY and properly fill the "advanced" menu. A very common mistake is to leave default conditions. Please assign a realistic channel loss.
03-25-2019 03:25 AM
Power voltages are in the valid range and i don't see glitches here. I'll try to perform experiments with insertion loss parameter.