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Visitor
Visitor
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Registered: ‎01-09-2020

Dip in eye scan using DFE (Kintex-7 GTX transceiver)

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Hi,

I am currently working on a function to automatically check eye mask compliance of a given serial interface using the eye scan feature of a GTX transceiver in a Kintex-7 FPGA. For this function I need the eye scan data to represent the signal at the input pins of the FPGA in the best possible way.

To ensure that the result is not manipulated by the automatic adaption functions of the transceivers, I've set the parameters of the equalization to fixed values using the override ports and the DRP. By now I've found a combination of parameters for the DFE mode that works pretty well (basically setting all TAPs to 0 or their neutral value and adjusting the amplifier for the given amplitude). Still there is a dip around 0 UIs in the eye scan as you can see in the attached picture.

The mentioned "dip" is not visible at the input of the FPGA. It is also not visible at any eye scan using LPM mode (picture attached). Since I would prefer the DFE mode for a couple of reasons: Do you have any recommendations on how to get rid of the dip in the DFE mode?

The AGC, CTLEs and the TAPs don't seem to really affect the dip. Changing the parameter for "voltage peak" does not seem to change anything, so I don't quite understand what this function does.

Thank you for your answers.

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DFE.JPG
LPM.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @philippcw-s ,

you are right. As you can see the dip mirrors depending on which UT sign is used. So this might be an artefact of the DFE transfer function.

You will probably only get a modified picture of the situation at the pins. There will always be circuitry between the pins and the measure point. So, you would have to live with an approximation.

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Adventurer
Adventurer
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Registered: ‎12-27-2018
Hi Philip
 
Your IBERT has a wide open eye!!!
I suppose you don’t see bit errors with this perfect eye.
Don’t bother the dip, as long as no bit error.
Maybe this is the limit of GTX RX performance??
 
Best regard.
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @philippcw-s ,

I guess this dip is coming from the DFE eye scan method. For a DFE eye scan you have to do two scans and overlay them. This is caused by the used structure for the samplers. The is only one sampler for eye scan but two are used for the DFE setup, UT+ and UT-. To do a complete scan for DFE you need to do a scan for both sides.

With IBERT you would get both scans done together automatically. If you would do a manual scan you could look at both scans separately and compare.

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Visitor
Visitor
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Registered: ‎01-09-2020

Hi @eschidl,

thank you for your answer!

I use a design based on XAPP1198, so I've been able to capture two eyescans using only one of the ut signs. Unfortunately both eyescans show the same dip as the combined one before.

1.PNG
2.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @philippcw-s ,

you are right. As you can see the dip mirrors depending on which UT sign is used. So this might be an artefact of the DFE transfer function.

You will probably only get a modified picture of the situation at the pins. There will always be circuitry between the pins and the measure point. So, you would have to live with an approximation.

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View solution in original post