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Contributor
Contributor
260 Views
Registered: ‎06-25-2012

Does implementation schematic show actual GT connectivity?

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In Kintex UltraScale+ I have a GT reference clock arriving in Quad 224 to be shared between Quad 224 and Quad 225.

In the implementation schematic, the clock is directly connected to GTREFCLK00 of GTYE4_COMMON_X0Y1 (Quad 225), and GTNORTHREFCLK/GTSOUTHREFCLK are all tied to GND. I would expect that it would be connected to GTNORTHREFCLK instead, since the clock is coming up from Quad 224 (i.e. GTYE4_COMMON_X0Y0).

Does the schematic view not accurately represent the connections? Is this expected behavior?  (I'm using Vivado 2017.4)

The design is implementing through bitstream without any (related) DRC errors, but I have not yet tested it.

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Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎06-01-2017

Re: Does implementation schematic show actual GT connectivity?

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Your observation is expected behavior. When there is only one external reference clock, the implementation tool will automatically perform the clock routings for you.
See UG576 page 33 and Figure 2-7.

-------------------

From UG576:

Figure 2-7 shows a single external reference clock with multiple transceivers connected to
multiple Quads. The user design connects the IBUDFS_GTE3 output (O) to the GTREFCLK0
ports of the GTHE3/4_COMMON and GTHE3/4_CHANNEL primitives for the GTH transceiver.
In this case, the Xilinx implementation tools make the necessary adjustments to the
north/south routing as well as pin swapping necessary to route the reference clocks from
one Quad to another when required.

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Don’t forget to reply, kudo, and accept as solution.
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2 Replies
Xilinx Employee
Xilinx Employee
241 Views
Registered: ‎06-01-2017

Re: Does implementation schematic show actual GT connectivity?

Jump to solution

Your observation is expected behavior. When there is only one external reference clock, the implementation tool will automatically perform the clock routings for you.
See UG576 page 33 and Figure 2-7.

-------------------

From UG576:

Figure 2-7 shows a single external reference clock with multiple transceivers connected to
multiple Quads. The user design connects the IBUDFS_GTE3 output (O) to the GTREFCLK0
ports of the GTHE3/4_COMMON and GTHE3/4_CHANNEL primitives for the GTH transceiver.
In this case, the Xilinx implementation tools make the necessary adjustments to the
north/south routing as well as pin swapping necessary to route the reference clocks from
one Quad to another when required.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Contributor
Contributor
215 Views
Registered: ‎06-25-2012

Re: Does implementation schematic show actual GT connectivity?

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Yes, thanks, I had seen that in the User Guide, but was a little surprised that the Implementation schematic did not accurately reflect actual routing/connectivity (as would be present in the device itself).

 

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