04-11-2019 04:30 AM
I am trying to dynamically change the bitrate from 12.5GBit/s to 10Gbit/s
I followed the instruction from UG578:
To ensure all attributes are covered, Xilinx recommends generating wrappers from the UltraScale FPGAs Transceivers
Wizard at the desired line rates and comparing all the attributes for differences, then writing the corresponding values via DRP when switching between different line rates.
In simulation it works fine but on hardware fails.
After configuring all related registers I am using the gtwiz_reset_all_in of the reset helper block but the QPLL wont lock.
I am using 4 lanes which are distributed accross 4 Transceiver Quads. This means 4x QPLL.
The dynamic switch is applied to all quads in parallel.
04-12-2019 02:36 AM
before writing to an address of DRP, did you first read the address and make sure you only changed required bits and keep the remaining bits untouched?
you write 16bit to an address at a time. sometimes you only change one or two bits. so you need to make sure the remaining bits are unchanged. That's why you need to read before attemping to write.
04-12-2019 02:47 AM
What i actually do is - first identified the different settings then in a next step i read the whole content of that register address. Thereby i am not doing read modify write transactions but only write to the whole associated register address.
That is how it works in simulation.
On hardware changing to bitrate 6.25 (which is half the rate) without modifying the qpll settings also works fine - via drp.
04-15-2019 01:18 AM
when you got failure from 12G to 10G, you can go back to 12G by writing DRP.
Does QPLL lock after it returns to 12G?