Dynamic data rate switching for the same gty quad.

[yogesh_tripathi]

Hi,
I'm trying to use a gty quad to switch between to data rate 6.25 and 3.125 Gbps with gtref clock 156.25Mhz.

Is it possible?

Possible with single gtrefclock of 156.25Mhz?  

[zhendon]

@yogesh_tripathi

That's completely possible. 

3.125Gbps is just half of 6.25. So it may only need you to change the output divider. for tx, it's txout_div. For rx, it's rxout_div.

The best way is to generate the wrappers from serdes wizard with the desired line rate and then compare all the attributes for differences. After knowing all the differences, you can then write the corresponding values through DRP registers.

[yogesh_tripathi]

hi @zhendon,

Got your point. Just want to confirm that setting drp reg <TX_OUT_DIV> from 1 to 2 will do?

GT wizard is first configured as :

1> four channel tx @6.25Gbps with ref clock 156.25Mhz.

2> 8b/10b enabled. 40bit internal width.

Ip gives usrclk1/2 as same 156.25 for 6.25Gbps

while for 

1> four channel tx @3.125Gbps with ref clock 156.25Mhz.

2> 8b/10b enabled. 40bit internal width.

Ip gives usrclk1/2 as same 78.125 for  3.125Gbps.

[yogesh_tripathi]

compared drp reg value for both data rate in example design.
tx_out = 0 for 6.25Gbps
and tx_out = 1 for 3.125.

[zhendon · Accepted solution]

Hi @yogesh_tripathi

if output divider is the only difference, you can also use tx/rxrate port to initiate a rate change.

You can find detail information in GTY user guide UG578 and search with key word txrate or rxrate. You won't miss it.

This would be easier than a drp register access. 

[yogesh_tripathi]

txrate port works.
Thank-you for your expertise.

[yogesh_tripathi]

Hi @zhendon,

Everything was fine with dynamic data rate switching between 6.25Gbps/3.125Gbps using Txrate port.

Instantiated GTY ip for 6.25Gbps line rate and set the txrate(2:0) = 001 for 6.25Gbps (usrclock2 =156.25Mhz) and  txrate(2:0) = 010 for 3.125Gbps(usrclock2= 78.125Mhz).

But when tried for 1.25Gbps with txrate(2:0) = 001, usrclk2 port gives 125Mhz clock.

According to eq3-1 of ug578 , txusrclock rate =linerate/internal datapath width.

for my case 1250/40 i.e 31.25.

On generating example design for same ip configuration found that txrate port is assigned "ZZZ".

and usrclock2 was also right i.e 31.25.

Are there any other attributes need to be take care of which can clear this doubt.