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kleinkuang
Visitor
Visitor
1,329 Views
Registered: ‎12-03-2017

Dynamic switching between QPLL0 and QPLL1

Hi all,

 

I met some issues when using QPLL0 and QPLL1 at the same time

 

As QPLL0 and QPLL1 have limited VCO Operating Range (GHz)

QPLL0 9.8–16.375
QPLL1 8.0–13.0

And we want to generate PRBS with line rate among a range between 10~30 Gbps, I want to dynamically switch QPLLs for generating PRBS with adjustable line rates.

 

When customizing the Transceiver Wizard: (use the same project I developed and have enabled secondary QPLL)

(switch qpll1 through controlling TXSYSCLKSEL, RXSYSCLKSEL, TXPLLCLKSEL, RXPLLCLKSEL and then reset all)

 

EXP1: If I select both QPLL0 for Rx and Tx, the PRBS checker is error free (all channels RXPRBSLOCKED=1). But when I switch to QPLL1, the checker does not work anymore (RXPRBSERR=0, RXPRBSLOCKED=0)

 

EXP2: If I select both QPLL1 for Rx and Tx, the checker does not work initially as the default QPLL is QPLL0. When I switch to QPLL1, the same way as EXP1, the checker works fine.

 

EXP3: If I select QPLL0 for Tx and QPLL1 for Rx, neither QPLL0 and QPLL1 work, but I read the output of QPLL, both QPLL0LOCK and QPLL1LOCK are HIGH which indicates that the QPLL0/1 frequency is within the predetermined tolerance.

 

I want to ask if it is doable to dynamically switch between QPLL0 and QPLL1 and if there is a guide available

 

Thanks a lot!

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2 Replies
borisq
Xilinx Employee
Xilinx Employee
1,290 Views
Registered: ‎08-07-2007

in example 1, after switching QPLL0 to QPLL1, is fsm_reset_done asserted on both tx and rx? it seems the checker is hold in reset. the rx fsm may not complete. 

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venkata
Moderator
Moderator
1,191 Views
Registered: ‎02-16-2010

I hope you have the design setup such that reference clock is connected to both QPLLs.

Which ports do you control to switch between QPLLs?
Do you reset the GT after the switching?
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