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200 Views
Registered: ‎04-30-2019

Example design for GTY Wizard fails to fully define IO causing tool errors

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So having done a quick search, this seems like a common error that has been going on for a long time without a fix.  In my case, I'm using the VCU108 and generating an example design from the GTY transceiver wizard.

The generated design has 5 signals, hb_gtwiz_reset_all_in, link_down_latched_out, link_down_latched_reset_in, link_status_out, and hb_gtwiz_reset_clk_freerun_in, that are left unconstrained in the top level XDC file, gtwizard_ultrascale_0_example_top.xdc.  In fact that are placeholders for the signals with a comment to uncomment the constraints and assign "appropriate pin locations for your board".

I would have thought that an example design for a defined eval board would have had all the IOs defined.  Can someone assign a bug on your dev team to fix this.  It's been around since at least 2015 after searching the forums.

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Xilinx Employee
Xilinx Employee
166 Views
Registered: ‎08-07-2007

回复: Example design for GTY Wizard fails to fully define IO causing tool errors

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hi shareef@phoelex.com 

 

The idea is great for designs targeting Xilinx eval boards. 

We can communicate this to development. 

 

Thanks,

Boris

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Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎08-07-2007

回复: Example design for GTY Wizard fails to fully define IO causing tool errors

Jump to solution

hi shareef@phoelex.com 

 

The idea is great for designs targeting Xilinx eval boards. 

We can communicate this to development. 

 

Thanks,

Boris

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Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
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93 Views
Registered: ‎04-30-2019

Re: Example design for GTY Wizard fails to fully define IO causing tool errors

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I had someone ask me how I solved this so I'll document it here for future searches.  It's specific to the board you are using but in my case I'm using the VCU108.  The steps to follow are:

1.  Identify which clock input your board uses.  If it's a differential input, then you'll need to instantiate an IBUFDS in the example_top.v.  Note that hb_gtwiz_reset_clk_freerun_in changes to hb_gtwiz_reset_clk_freerun_in_n/p.

  // ===================================================================================================================
  // BUFFERS
  // ===================================================================================================================

  // Buffer the hb_gtwiz_reset_all_in input and logically combine it with the internal signal from the example
  // initialization block as well as the VIO-sourced reset
  wire hb_gtwiz_reset_all_vio_int;
  wire hb_gtwiz_reset_all_buf_int;
  wire hb_gtwiz_reset_all_init_int;
  wire hb_gtwiz_reset_all_int;

  IBUF ibuf_hb_gtwiz_reset_all_inst (
    .I (hb_gtwiz_reset_all_in),
    .O (hb_gtwiz_reset_all_buf_int)
  );

  assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int || hb_gtwiz_reset_all_vio_int;

  // Globally buffer the free-running input clock
   wire hb_gtwiz_reset_clk_freerun_in;
   wire hb_gtwiz_reset_clk_freerun_buf_int;

  IBUFDS 
    u_clkin (
             .I  (hb_gtwiz_reset_clk_freerun_in_p),
             .IB (hb_gtwiz_reset_clk_freerun_in_n),
             .O  (hb_gtwiz_reset_clk_freerun_in)
             );

  BUFG 
    bufg_clk_freerun_inst (
			   .I (hb_gtwiz_reset_clk_freerun_in),
			   .O (hb_gtwiz_reset_clk_freerun_buf_int)
			   );
   

2.  Modify the XDC file for the new clock pin name

create_clock -name clk_freerun -period 8.0 [get_ports hb_gtwiz_reset_clk_freerun_in_p]

3. Identify which LEDs and GPIO you are going to use for any other signals such as the link_* signals in the original post.  Open the schematic of the board and get the net names of the nets connected to the pins.  You can then use the 'set_property BOARD_PIN' syntax to set the location constraint.

# CLK_125MHZ_N
set_property package_pin BC8 [get_ports hb_gtwiz_reset_clk_freerun_in_n]
set_property iostandard LVDS [get_ports hb_gtwiz_reset_clk_freerun_in_n]

# CLK_125MHZ_P
set_property package_pin BC9 [get_ports hb_gtwiz_reset_clk_freerun_in_p]
set_property iostandard LVDS [get_ports hb_gtwiz_reset_clk_freerun_in_p]

# CPU_RESET
set_property package_pin E36     [get_ports hb_gtwiz_reset_all_in]
set_property iostandard LVCMOS12 [get_ports hb_gtwiz_reset_all_in]

# 5 Way Button Pad
set_property BOARD_PIN {GPIO_SW_C} [get_ports gpio_buttons[0]]
set_property BOARD_PIN {GPIO_SW_W} [get_ports gpio_buttons[1]]
set_property BOARD_PIN {GPIO_SW_S} [get_ports gpio_buttons[2]]
set_property BOARD_PIN {GPIO_SW_E} [get_ports gpio_buttons[3]]
set_property BOARD_PIN {GPIO_SW_N} [get_ports gpio_buttons[4]]

# LEDs
set_property BOARD_PIN {GPIO_LED_0_LS} [get_ports gpio_led_user[0]]
set_property BOARD_PIN {GPIO_LED_1_LS} [get_ports gpio_led_user[1]]
set_property BOARD_PIN {GPIO_LED_2_LS} [get_ports gpio_led_user[2]]
set_property BOARD_PIN {GPIO_LED_3_LS} [get_ports gpio_led_user[3]]
set_property BOARD_PIN {GPIO_LED_4_LS} [get_ports gpio_led_user[4]]
set_property BOARD_PIN {GPIO_LED_5_LS} [get_ports gpio_led_user[5]]
set_property BOARD_PIN {GPIO_LED_6_LS} [get_ports gpio_led_user[6]]
set_property BOARD_PIN {GPIO_LED_7_LS} [get_ports gpio_led_user[7]]

# UART
set_property BOARD_PIN {USB_UART_RX} [get_ports uart_rxd]
set_property BOARD_PIN {USB_UART_TX} [get_ports uart_txd]


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