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Explorer
Explorer
649 Views
Registered: ‎09-08-2009

FPGA clock input

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If FPGA has a high speed (GHz) external interface, is there any suggestion for FPGA clock input frequency (reference input clock for PLL)

  • should it be LVDS instead of single ended
  • can it be low frequency as 20MHz or is it suggested to have high frequency like 200MHz

 

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Adventurer
Adventurer
566 Views
Registered: ‎12-20-2010

Re: FPGA clock input

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The MGT reference clock must have very low jitter.  For this reason, it is not recommended to use a FPGA internal PLL to generate the reference clock.

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Adventurer
Adventurer
582 Views
Registered: ‎12-20-2010

Re: FPGA clock input

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Your MGT transceivers require a reference clock that is typically greater than 100MHz.   The exact frequency depends on what function are using the transceivers to perform, Ethernet, chip-to-chip bridge, etc.   When must specify the reference clock frequency when you add the core to your design and configure it in Vivado.

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Explorer
Explorer
571 Views
Registered: ‎09-08-2009

Re: FPGA clock input

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@kinkeads thank you for your reply.

Can I supply this 100MHz+ clock frequency using the Xilinx PLL and feeding the internal PLL with external 25MHz clock input?

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Adventurer
Adventurer
567 Views
Registered: ‎12-20-2010

Re: FPGA clock input

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The MGT reference clock must have very low jitter.  For this reason, it is not recommended to use a FPGA internal PLL to generate the reference clock.