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Observer alexeytea
Observer
277 Views
Registered: ‎09-17-2018

Failed clock routing for Kintex Ultrascale+ GTH transceiver

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Hello!

I am trying to implement a GTX transceiver in the Kintex U+ (xcku5pffv900).

Differential source clock coming to the pins Y5/Y6 (bank 225), there I connect them to the IBUFDS_GTE4 and the output clock from here is connected to the GTX refclk_in.
But after implementation vivado (2018.3) is inferring a BUFGCE between IBUFDS_GTE4 and GTX, hence it fails to route it. 
The error is "The IBUFDS_GTE4 O pin may only be connected to the GTREFCLK pin of a GTE4_CHANNEL. The IBUFDS_GTE4 O pin cannot drive gtye4_channel_gen./../../../GTYE4_CHANNEL_PRIM_INST."

I tried to use an example design with the same clk input pins. There the IBUFGDS_GTE4 is connected the same way as I did in my design. But there no BUFGCE is inferred and the implementation finishes without warnings. No extra commands in the xdc file are written.

I've also added "set property CLOCK_BUFFER_TYPE NONE" in my xdc, but it did not help.

Any suggestions?

Top hdl file is just connected instances of IBUFDS_GTE4, gtwizard_wrapper and my ip core.

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Xilinx Employee
Xilinx Employee
182 Views
Registered: ‎10-19-2011

Re: Failed clock routing for Kintex Ultrascale+ GTH transceiver

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Hi @alexeytea ,

if you want to use the reference clock input as the free running system clock, you would need to connect it through the ODIV2 output of IBUFDS_GTE4 to fabric. The 'O' output can only drive the transceiver primitives refclk inputs.

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Observer alexeytea
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263 Views
Registered: ‎09-17-2018

Re: Failed clock routing for Kintex Ultrascale+ GTH transceiver

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And, of course, only after writing this post I figured out that in the example design gtwiz_reset_clk_freerun_in and gtrefclk_in is two separate clocks, and the  gtwiz_reset_clk_freerun_in is going through the BUFGCE buffer. I just connected both of them to the output of IBUFDS_GTE4.

Adding the buffer between reset clk and the IBUFDS_GTE4 did nothing. But without reset clk at all implementation goes fine.

So the question now is: how can I clock reset helper block from mgtrefclk or, if it is not possible, do I really need that block? 

UPDATE: well, considering the debug core could not detect usrclk from GTX and my logic block outputs nothing, it is safe to assume that I need this init/reset helper block. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: Failed clock routing for Kintex Ultrascale+ GTH transceiver

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Hi @alexeytea ,

if you want to use the reference clock input as the free running system clock, you would need to connect it through the ODIV2 output of IBUFDS_GTE4 to fabric. The 'O' output can only drive the transceiver primitives refclk inputs.

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