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Visitor
Visitor
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Registered: ‎12-19-2018

GHT Reference Clock

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Hello,

I am working on a project with the UltraScale XCKU060 family and need to use the GTH Transceiver for raw data ( no encoding).

I have some questions about MGT Refclock:

 

1) Is it estrictly necessary an external clock source for the GTH Reference Clock?

2) If necessary, how should the frequency be calculated for a line rate of 0.5 to 2 Gbps?

I've read the UG(576), UG(572), PG(182) and couldn't find the answer. 

 

Thank you very much.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @jboggiano ,

yes, the reference clock signal needs to be differential.

The reference clock inputs are specific inputs for the transceivers. They are not related to SelectIO/Global Clock Inputs.

Figure 5-3 shows both lines of the differential signal as they have by itself some single ended properties. But they are still one differential signal.

If you go down in the user guide to figure 5-7 and 5-8 you can see two possibilities to connect the reference clock inputs.

The inputs do not have a specific IO standard (and you cannot select one in the constraints).

Please follow the recommendations for the reference clock in this chapter and the specifications from the datasheet.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @jboggiano ,

yes, you need to use an external source.

If you look in UG576 in the chapters for CPLL and QPLL under 'Shared Features', you will find the equations necessary. You also find the possible divider settings here.

But you could also open a project for your device in Vivado and open the transceiver wizard from IP catalogue. In the wizard you put in your line rate and select the PLL to use. Then the wizard gives you all possible reference clock frequencies for selection in the drop down menu.

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Visitor
Visitor
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Registered: ‎12-19-2018
Thank you so much for your accurate an so fast response Eschidl! I reviewed the UG576, Equations 2-1 and 2-2 and checked them with the GTH Wizard.

Does this external ref clock need to be differential strictly?

On Chapter 5 "Board Design Guidelines" Figure 5-3 shows a Single-Ended Clock Input Voltage Swing. However I didn't find a "Reference Clock Input pins/pads" that shows how to connect a single-ended clock source instead.

Moreover, on UG572 says that "global clock pins can be connected to a differential or single-ended clock on the PCB. Single-ended clock inputs must be assigned to the P (master) side of the GC input pin pair."

There is no information such as this on UG576.

Would you clarify this for me please?

Thank you so much!

Juan.
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Xilinx Employee
Xilinx Employee
549 Views
Registered: ‎10-19-2011

Hi @jboggiano ,

yes, the reference clock signal needs to be differential.

The reference clock inputs are specific inputs for the transceivers. They are not related to SelectIO/Global Clock Inputs.

Figure 5-3 shows both lines of the differential signal as they have by itself some single ended properties. But they are still one differential signal.

If you go down in the user guide to figure 5-7 and 5-8 you can see two possibilities to connect the reference clock inputs.

The inputs do not have a specific IO standard (and you cannot select one in the constraints).

Please follow the recommendations for the reference clock in this chapter and the specifications from the datasheet.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

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Visitor
Visitor
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Registered: ‎12-19-2018

Thank you @eschidl for your support! 

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Contributor
Contributor
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Registered: ‎05-07-2017

I am using MPSOC 15eg, the reference clock for GT lane0 can not get locked. the read of 0xfd4023e4 (pll lock status register) always returns 0x01.

Does the PLL lock of reference clock all done by hardware, any settings we can make by software to make it work?

the reference clock single end peak-to-peak voltage is about 180mV, does it high enough? 

 

==v=i=v=o==
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