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Explorer
Explorer
430 Views
Registered: ‎08-04-2016

GT transceiver wizard clocking

Hello,

I want to understand the clocking infrastructure while using the GT transceiver wizard(Ultrascale).

I'm using the ZCU106 board and writing an HDMI transmitter. The GTREFCLK0 input is connected to an output from Si5324 on the board. So, as I understand it, the Si5324 needs to be programmed to generate a reference clock for the GT. I'm programming this to 148.5 MHz.

What should be done next? There are multiple clock outputs from the GT transceiver wizard IP (txusrclk, txusrclk2, qpll0_clk). Which of these should I use as my pixel clock?

I would like to dynamically program (DRP) the pixel clock based on the resolution required. Which document lists the frequency relationship between the input and output clocks? Is there a reference design to run DRP from SDK to change the clocks?

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6 Replies
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Explorer
Explorer
410 Views
Registered: ‎03-16-2019

Re: GT transceiver wizard clocking

Hi,

ug576 ultrascale GTH transceivers is a good document for you. look at page 314 and 315

https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf

 

 

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Adventurer
Adventurer
403 Views
Registered: ‎05-07-2018

Re: GT transceiver wizard clocking

Hi,

for the HDMI transmitter, I suggest you generate HDMI Tx or Rx example design and survey the example. 

I think if you use HDMI IP core or vid_phy_controller you can reach your purpose easily. 

 

 

hdmi.PNG
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Explorer
Explorer
345 Views
Registered: ‎08-04-2016

Re: GT transceiver wizard clocking

Hi

@behnam_2705newThanks. That checks out with what I have been getting in simulation.

In my design, the datawidth is 20 bits and both rxusrclk and rxusrclk2 are half the pixel clock frequency. I would also like to get the pixel clock frequency out from the GT, if possible. I notice that the qpll0refclkout is the right frequency but I don't think this can be routed into the fabric. Any ideas?

@ghasemi_rUsing the HDMI Tx/Rx subsystem IPs is not really an option for me. And since the video phy controller is said not to support standalone operation, I don't think I can use it either. Essentially, I would like to implement the functionality of the video phy controller. Any idea where the tmds_clock and video_clock are derived from.

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Explorer
Explorer
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Registered: ‎03-16-2019

Re: GT transceiver wizard clocking

HI,

check the table 4-48 on that document.

your Interface Width and RX_DATA_WIDTH are important to be considered.

The Rxuserclk rate is calculated with a formula.

Capture.PNG

check the Capture.PNGtable to find out your Internal Data width

 

and the relation between Rxusrclk and Rxusrclk2 is computed with the Capture.PNGtable.

 

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Explorer
Explorer
317 Views
Registered: ‎08-04-2016

Re: GT transceiver wizard clocking

In my case, the internal and external datawidth are set to 20, which is fine. rxusrclk=rxusrclk2

But I'm generating data 10 bits at a time and have a gearbox. So I need double the rxusrclk. Currently I'm using an MMCM to generate it. Is there a way to get it out of the GT itself?

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Explorer
Explorer
282 Views
Registered: ‎03-16-2019

Re: GT transceiver wizard clocking

based on my knowledge, GT generates clock by line rate and their data width which you have selected in the IP wizard.

why don't you generate 20-widths data?