01-15-2018 06:33 AM
I am using vc709 evaluation board and Vivado 2015.2. I configured 3 cpri IP cores using Xlinx Transceiver IP core (GTH)( The IP core summary is attached). Then, I used the Xilinx IP example design for my implementation. In the example design, I kept the Frame generator and checker for GTH1. GTH0 and GTH2 are looped backed internally using asynchronous FIFO and not connected to frame generator and checker.
As ug887 clearly mentioned, “The VC709 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the board. FPGA user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin AW32 and REC_CLOCK_C_N, FPGA U1 pin AW33) for jitter attenuation. The jitter-attenuated clock (Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTH Quad 113 inputs MGTREFCLK0P (FPGA U1 pin AH8) and MGTREFCLK0N (FPGA U1 pin AH7). I used Jitter-Attenuated Clock ( Si5324) “. Therefore, I modified the Xilinx GTXE2 (figure is attached), which is available in XTP241 associated Files, and used the Si5324 to create the reference clock.
After implementation, I considered 4 test scenarios using 850nm transceiver(s) and fibres.
ILA clearly shows that the frame checker receives the generated frames, which are cpri iq samples, without any errors.
After these tests, I used an Analyser ( Anritsu MT1100A Network Master Flex) to test the design using GTH0 internal FPGA loopback. I can see the Analyser is sending, but doesn’t receive the frames.
I also set the loopback parameter for this GTH to “100”( Far-End PMA loopback). Again, the Analyser doesn’t receive the frames.
Could you please advise me what is the issue might be?
Thanks for your time.
01-23-2018 05:15 AM
Yes, I did it. Also, I have tried board to board test. Basically, one board loopback is working but board to board is not working. I am not sure, but I think tx and rx clocks have an issue and I need a clock recovery system.
01-25-2018 01:59 PM - edited 01-25-2018 02:00 PM
The input to Si5324 should be the recovered clock (RXOUTCLK), which you can send by RXOUTCLK -> BUFG -> ODDR -> OBUFDS.
In your drawing, the input comes from a local oscillator through an MMCM.
01-29-2018 04:21 PM
For far-end PMA loopback, TX_XLK_SEL must be set to TXOUT. TXPIPPMEN set to 0, and TXPIPPMSEL set to 0. GTTXRESET is required after entering and exiting far-end PMA loopback. Can you check if your design is consistent with these loopback requirements?
01-30-2018 01:31 PM
Yes , it does.
As I mentioned before, I tried a board to board test. Basically, one board loopback is working but board to board is not working.
I tried another scenario for my board to board test. I used a common external ref clock for both boards. I can see everything is working fine. It is working with external ref clock , but doesn't work with internal one. There should be a problem with clock recovery. The recovery clock system path is :
RXOUTCLK -> BUFG -> ODDR -> OBUFDS -> Si5324
si5324 -> IBFDS_GTE2 -> BUFG -> TXUSRCLK,TXUSRCLK2, RXUSRCLK, RXUSRCLK2
Do you have any idea what the problem is?
01-30-2018 04:04 PM
RXOUTCLK -> BUFG -> ODDR -> OBUFDS -> Si5324 (you already have this path)
si5324 -> IBFDS_GTE2 -> GTREFCLK (drive the output of si5324 to the GT REFCLK pin)
RXOUTCLK -> BUFG -> RXUSRCLK/RXUSRCLK2 (use RXOUTCLK to drive RXUSRCLKs)
TXOUTCLK -> BUFG -> TXUSRCLK/TXUSRCLK2 (use TXOUTCLK to drive TXUSRCLKs)
01-31-2018 12:13 PM
Can you check if the reference clock is valid and runs at the correct frequency (122.88MHz)? See if you can probe at both the input and output of Si5324.
Which GTH Bank are you using? The jitter attenuated clock only routes to MGTREFCLK0 of bank 113 (CHANNEL X1Y12 to X1Y15).
Do you have any other GT status signal in your ILA that indicates QPLLLOCK, TX/RXRESETDONE, etc?
02-01-2018 02:03 AM - edited 02-02-2018 02:10 AM
I monitored the Si5324 input and output by an oscilloscope using SMA . I have attached the figures. Fig 1 is the Si5324 ouput and Fig 2 is the Si5324 input.
I use DSP LLSim to calculate the Si5324 registers value. I have attached the reg value txt file. The desired value is 122.88MHz , but I can see 119.4 MHz.
Status signals are all fine and I'm using bank 113 (CHANNEL X1Y12 to X1Y15).
02-06-2018 04:38 PM
I am not sure where the discrepancy is resulting from, but my DSPLLsim startup wizard yielded different register values compared to yours. Also, there is only one input to the Si5324 on the VC709 board.
Attached my exported register map. Can you try with these values?
02-09-2018 10:52 AM
That is unexpected...In the DSPLLsim wizard, I did set for 122.88 -> 122.88. Are you able to read back the registers to see if the correct values went through?
02-11-2018 01:41 AM - edited 03-24-2018 09:07 PM
Yes, I use Xilinx reference design and I can read back the register values.
Are you using vc709? Could you please send me the design and code you tried? I can send you the design if you would like .