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239 Views
Registered: ‎01-17-2018

GTH FAR END PCS LOOPBACK issue

Hi,

I am Krishnachaitanya using GTH Transceiver IP core and trying to do far end pcs loop-back test using "Two" KCU105 FPGA Ultra-scale Boards.

B1 (Board 1) : Master. It will generate PRBS patterns internally.

B2 (Board 2) : Slave. It will receive PRBS patterns from Board 1. It will send the same received data through TX ports by setting  LOOPBACK value = "110" (6) .

I Connected B1 (Board 1) TX pairs to B2(Board 2) RX pairs and vice versa.

Here, My B1 will generate prbs patterns internally and transmitted through a TX pairs and  B2 (Board 2) will receive this data & sent it back to B1 using loopback value = "100" (4-Far end PMA loopback) or "110" (6-Far end PCS loopback).

It is working for loopback value = "100" (4-Far end PMA loopback) and not working for loopback value = "110" (6-Far end PCS loopback).

Please guide me how to resolve this issue.

Note: In Simulation it is working.

 

Thanks and regards

Krishnachaitanya G

 

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10 Replies
197 Views
Registered: ‎01-17-2018

Re: GTH FAR END PCS LOOPBACK issue

Hi,

I am eagerly waiting for reply..

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Xilinx Employee
Xilinx Employee
185 Views
Registered: ‎03-30-2016

Re: GTH FAR END PCS LOOPBACK issue

Hello c.gannamani@gmail.com

XF_FE_PCS_LOOPBACK.png

Do you use the same REFCLK source for BOARD1 and BOARD2 ??
If not Far-End PCS loopback will not work (this is expected result), since PRBS pattern does not have clock-correction codes.

Thanks & regards
Leo

Xilinx Employee
Xilinx Employee
177 Views
Registered: ‎08-07-2007

回复: GTH FAR END PCS LOOPBACK issue

hi c.gannamani@gmail.com

 

your observation is expected.

In this case, B1 and B2 are operating at different frequency. There are PPM frequency offset between the two.

In Far End PCS Loopback mode, there is no way to solve this offset with PRBS pattern because clock correction cannot work without pre-defined clock correction symbols.

In Far End PMA Loopback mode, the trasmitter is operating at recovery clock frequency thanks to TX PI. so this PPM offset is natually solved inside GT.

 

Thanks,

Boris

 

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169 Views
Registered: ‎01-17-2018

回复: GTH FAR END PCS LOOPBACK issue

Hi Boris/Leo

It means I need to provide the reference clock externally using a signal generator to both the boards (B1 & B2) right?

 

Thanks

Krishnachaitanya

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Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎03-30-2016

回复: GTH FAR END PCS LOOPBACK issue

Hello Krishnachaitanya c.gannamani@gmail.com

Yes, your understanding is correct.

Regards,
Leo

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Xilinx Employee
Xilinx Employee
132 Views
Registered: ‎08-07-2007

回复: GTH FAR END PCS LOOPBACK issue

hi c.gannamani@gmail.com

 

yes, you are correct. 

using the same clock source will eliminate the PPM frequency offset between RX part and TX part.

You also need to eliminate the phase offset between the two by connect a common BUFG_GT to TXUSRCLK and RXUSRCLK, TXUSRCLK2 and RXUSRCLK2.

 

Gearbox should be disabled as well.

 

Thanks,

Boris

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115 Views
Registered: ‎01-17-2018

回复: GTH FAR END PCS LOOPBACK issue

Hi Boris,

 

 I. How can I connect a common BUFG_GT to TXUSRCLK and RXUSRCLK, TXUSRCLK2 and RXUSRCLK2 to eliminate the phase offset between the two Boards.

And 

 II. Providing a same reference clock to both the boards using external clock generator means

          1. Signal generator with double differential outputs ( one differential pair for B1 & another differential pair for B2) ?

                                                                                                  OR

          2. Signal generator with only one differential output, then using a splitter feed it to both the boards ?

    Which process is correct?

Thanks

Krishnachaitanya

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Xilinx Employee
Xilinx Employee
95 Views
Registered: ‎08-07-2007

回复: GTH FAR END PCS LOOPBACK issue

hi c.gannamani@gmail.com

I. How can I connect a common BUFG_GT to TXUSRCLK and RXUSRCLK, TXUSRCLK2 and RXUSRCLK2 to eliminate the phase offset between the two Boards.

- You do this on the board which is set to Far end PCS loopback. You don't need to do this on the other one. The purpose to do this, is to eliminate the phase offset between RX PCS and TX PCS of the GT which is in Far End PCS Loopback mode.

 

 

II. Providing a same reference clock to both the boards using external clock generator means

          1. Signal generator with double differential outputs ( one differential pair for B1 & another differential pair for B2) ?

                                                                                                  OR

          2. Signal generator with only one differential output, then using a splitter feed it to both the boards ?

    Which process is correct?

- I think process 1 is commonly correct. Please make sure the two outputs come from the same oscillator.

In process 2, how does the splitter work? the routing of reference clock should not be stubbed.

 

Thanks,

Boris

 

 

 

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75 Views
Registered: ‎01-17-2018

回复: GTH FAR END PCS LOOPBACK issue

Hi Boris/Leo,

 

How can use the clock correction technique? What patterns i need to use?

Regards

Krishnachaitanya

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33 Views
Registered: ‎01-17-2018

回复: GTH FAR END PCS LOOPBACK issue

Hi,

Can you provide the clock correction patterns?

 

Thank you

Krishnachaitanya

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