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557 Views
Registered: ‎02-20-2008

GTH QPLL frequency range

I'm designing a JESD204B interface for the Kintex Ultrascale (xcku060-ffva1156-1-i) for a custom board. I'm changing the line rate with DRP.

Everything works fine up to 726MHz (ADC clock).

line rate = 7.26 Gbit/s;
f_reference = 363 MHz;
f_vco qpll0 = 14.52 GHz;
qpll0: D = 2, M = 1, N = 40
jesd : F = 2, K = 32, L = 4, M = 2, S = 2

But at 727MHz and higher QPLL can not lock.

line rate = 7.27 Gbit/s;
f_reference = 363.5 MHz;
f_vco qpll0 = 14.54 GHz;

According to DS892 QPLL0 frequency range is 9.8...16.375GHz for all speed grades.

Should I change any QPLL0_CFG registers as well? Regeneratig JESD Phy there are no any difference in these registers. However suddenly changing QPLL0_CFG2  I found QPLL get in lock at 14.54GHz and JESD working. But it stops locking at low frequencies.

What parameters can I try to set? Are there any description for QPLL0_CFG registers?

P.S. Design requires to keep VCO frequency = x2 lane rate.

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Xilinx Employee
Xilinx Employee
492 Views
Registered: ‎03-30-2016

Hello @evgeny_shumilov 


I don’t think there is any description/explanation on QPLL0_CFG register meaning since we recommend users to use QPLL setting from transceiver wizard as is without any modification.
I am not familiar with JESD204 , but I can double-check on GTH setting.


1. Could you please share the xci file of JESD204_PHY IP  to receive 7.26 Gbps input signal?

2. Could you please share what registers you have modified to receive 7.27 Gbps input signal?

 

Thanks
Leo

471 Views
Registered: ‎02-20-2008

Programming procedure for both speeds: 7.26 and 7.27Gbps. The difference is in reference clock.

I1)AXI-lite JESD204:
(power off)
A = 0x04; D = 0x1;
A = 0x08; D = 0x1;
A = 0x08; D = 0x1;
2) DRP interface MGT:
(qpll0_fbdiv)
A = 0x14; D = 0x26;
3) DRP interface MGT:
(qpll0_refclk_div)
A = 0x18; D = 0x808;
4) DRP interface MGT:
A = 0x63; D = 0x1;
5)AXI-lite JESD204:
(QPLL0 select)
A = 0x10; D = 0x3;
5)AXI-lite JESD204:
(power on)
A = 0x04; D = 0x0;
6)AXI-lite JESD204:
(reset on PLL + datapath)
A = 0x24; D = 0x1;
7)AXI-lite IP JESD204:
(reset off PLL + datapath)
A = 0x24; D = 0x0;

I can not remember nor repeat the sequence for QPLL0_CFG2 then Phy get working.

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Xilinx Employee
Xilinx Employee
456 Views
Registered: ‎03-30-2016

Hello @evgeny_shumilov 

 

I cannot check if your GTH DRP setting is good, without knowing the base transceiver configuration. 

Would you be able to share your JESD204_PHY xci ?

 

Regards
Leo

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454 Views
Registered: ‎02-20-2008

I'm sorry. xci did not attached correctly in previous post.

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Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎03-30-2016

Hello @evgeny_shumilov 

Thanks for sharing XCI file.
1. It seems your base configuration is 6.25Gbps
    BASE_CONFIGURATION_6250.png
2. I had a quick glance on your programming procedure and compared with PG198 guideline, I cannot find any issue.
3. But when I generated JESD204_PHY IP with 7.26Gbps and 7.27Gbps configuration, I found some QPLL0 parameter that need to be updated from your base IP configuration.
For example : GTHE3_COMMON_QPLL0_CFG4 = (16'b0000000000011011)

You may interested to read the following blog, to find the correct method changing transceiver line-rate dynamically.
https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/How-to-dynamically-change-UltraScale-UltraScale-GTH-GTY-line/ba-p/1116864

Regards
Leo