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Contributor
Contributor
566 Views
Registered: ‎09-06-2018

GTH QPLL lock simulation

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Hello,

I am simulating my serial link interface with a disruption on the clock reference in order to check if the QPLL stay locked.

Can I expect the same behavior between simulation and real life simulating the GTH IP, generated with the IP catalog, in the vivado simulator ?

Thank you,

Best regards,

Stéphane

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Xilinx Employee
Xilinx Employee
427 Views
Registered: ‎06-01-2017

Hi @sby38 

Any interruption to REFCLK can cause unknown effects since none of these behavior is characterized.

In practical terms, if this only happens on one clock cycle once in a very long time, the QPLLLOCK will likely stay asserted. Again, there is no guarantee that the data path would be intact, though for most cases it probably is.

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Contributor
Contributor
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Registered: ‎09-06-2018

Some additional information:

I am using vivado 2019.1 a Kintex Ultrascale FPGA.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Hi @sby38

If you change the REFCLK frequency to the extent that the PLL VCO/output frequency goes out of spec, or if you stop REFCLK, then you can see PLLLOCK deassert in simulation. However, the PLL behavior is analog and any analog behavior does not get modeled exactly in RTL simulation. The behavior that you see in simulation, for example, time it takes to deassert PLLLOCK, is going to be different on actual hardware. Even on the hardware, you may see different behavior across PVT (I mean for example lock time is not a fixed number, for example). It depends on what type of behavior are you looking to compare between simulation vs hardware.

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Contributor
Contributor
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Registered: ‎09-06-2018

Hello @jhua,

Thank you for your answer.

What if I have this behavior on the reference clock of the GTH ?

Will the QPLL unlock ?

sby38_0-1606291343551.png

In vivado simulator, the QPLL stays locked. I just need to resynchronize the link because the frame alignment is broken.

Regards,

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Hi @sby38 

The rising edges are used. Essentially the period/frequency is changed when this happens. It depends on how long and how often this happens, but this is an analog behavior which I would not recommend relying on how the verilog model behaves in this situation. Hardware will be different.

When REFCLK is not meeting spec (unstable), there is no guarantee that GT will continue to operate as spec'ed. When there is interruption to REFCLK, a full reset is required to guarantee GT operation. You may get away with not following this requirement, however, it's not guaranteed.

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Contributor
Contributor
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Registered: ‎09-06-2018

Hi @jhua,

This behavior can happen once considering the very long time between two occurrences.

The frequency will be exactly the same.

Can we expect that the QPLL will stay locked?

Or is it still not guaranteed?

Thank you again for your inputs!
Stephane 

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Xilinx Employee
Xilinx Employee
428 Views
Registered: ‎06-01-2017

Hi @sby38 

Any interruption to REFCLK can cause unknown effects since none of these behavior is characterized.

In practical terms, if this only happens on one clock cycle once in a very long time, the QPLLLOCK will likely stay asserted. Again, there is no guarantee that the data path would be intact, though for most cases it probably is.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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Contributor
Contributor
420 Views
Registered: ‎09-06-2018

Hello @jhua,

Thanks for all your feedbacks.

Have a good day.

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