cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
511 Views
Registered: ‎06-28-2019

GTH QPLL valid N values

Jump to solution

Hi,

Some background:

I'm designing a JESD204B interface for the Kintex Ultrascale (xcku115-flva1517-2-i). The interface will need to run at a number of different frequencies (about 10 different frequencies) which are dynamically configured. The transciever reference clock will need to be common for all interface frequencies so I want to work out the optimum reference clock value in order to get as close as possible to the interface frequencies I want to achieve. Obviously to calculate this I need to know all of the clock divider and feedback divider possibilities in the QPLL.

My question:

Playing around with the JESD204 PHY (4.0) wizard I've selected a reference clock of 122.88MHz to achieve a line rate of 6.4512Gbps. Looking at the generated IP files this has been achieved using an "N" value of QPLL0_FBDIV=105. However, the transciever user guide UG576 doesn't list 105 as a valid value. The values it lists are: 16, 20, 32, 40, 60, 64, 66, 75, 80, 84, 90, 96, 100, 112, 120, 125, 150, 160. So is UG576 out of date? Or have I missed something else? It would be really good to know all possible M, N and D values for the QPLL so that I can properly calculate the optimum reference clock without having to use the wizard and a "trial and error" method.

Thanks

Ed

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎11-29-2007

Hello Ed,

The new UG576 has been fixed and you will find the complete range or supported feedback divider values.

Thanks, kind regards,

Giovanni

View solution in original post

4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
482 Views
Registered: ‎11-29-2007

Hello,

for Ultrascale GTH QPLL0/1 the valid integer feedback divider N settings as shown in Figure 2-13, page 48 are 16, 20, 32, 40, 60, 64, 66, 75, 80, 84, 90, 96, 100, 112, 120, 125, 150, and 160.

Ultrascale+ GTH has integer feedback divider from 16 to 160 with no holes.

0 Kudos
Highlighted
473 Views
Registered: ‎06-28-2019

Thanks for getting back to me. You've confirmed what the documentation says, but my query is why I'm seeing different behaviour to the documentation.

Please can you explain why I am able to select feedback divider N settings which aren't what the documentation says? I have my Vivado project set up for the Kintex Ultrascale (so not an Ultrascale+ device) so surely the JESD204 PHY (4.0) wizard should only allow me to compile the IP with the Ultrascale values (not the Ultrascale+ values, which I understand are more comprehensive). In that case, how am I able to compile the IP for the Kintex Ultrascale and end up with a value of 105 for the feedback divider? It seems to be in direct conflict with the documentation.

Thanks

Ed

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
469 Views
Registered: ‎11-29-2007

Hello,

you are right the IP is in contrast with the UG. I need to verify this with the developers. Please give us some time to provide you an answer.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎11-29-2007

Hello Ed,

The new UG576 has been fixed and you will find the complete range or supported feedback divider values.

Thanks, kind regards,

Giovanni

View solution in original post