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eskull@0
Contributor
Contributor
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Registered: ‎11-10-2018

GTH RX/TX pins - what are they for???

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I have a really fundamental question about instantiating GTH transceivers (in this case, in KU060, down inside a 10GbE core). UG576 is not clear to me on this subject. 

The 10GbE core I am using has ports for rx and tx lines, that are wired from the underlying GTH core, that are brought out of the top-level file for the 10GbE core. Also, the GTH cores generated by the GTH wizard always has these rx/tx ports when I have run that tool. 

The UG576 user Interface port descriptions don't mention these rx/tx lines. The pin description table in UG576 (e.g., Table 5-1) lists MGTRXP(N) and similar for MGTTX, as the differential rx/tx pairs.

I read on the following forum (https://forums.xilinx.com/t5/Serial-Transceivers/GTH-GTY-LOC-constraints-package-pin-vs-channel/m-p/1048517) that rx/tx lines should be brought out to the top level of the FPGA design, even when assigning the MGT's via the X#Y# constraint (rather than pin constraints). Which is how I'm doing the instantiation (X#Y#).

Are these rx/tx lines actually the serial transceiver pin signals connected to the board? If not, how are these rx/tx lines used? 

 

Digging a bit deeper, on the board hardware I am testing with, there are no provisions (no pin connections to the baord) for the 16 port/pins I would need to actually bring these out, unless these are the actual serial transceiver signals. Running PAR with rx/tx ports in the top level but no pin assignments, the placer (I guess...) somehow assigns pins to these rx/tx ports. Comparing the pin assignments (impl io place report) with the schematic, it turns out the assigned pins are the corresponding transceiver rx/tx lines that connect the FPGA transceiver pins to the FMC connector to which the corresponding QSFP transceiver signals are connected to.

So my questions:

-To make sure I am not off in the weeds here, are these rx/tx signal lines the actual GTH rx/tx pin signals?

-And, is it correct (and required ?) to route these rx/tx signals to top level ports in the design, and then NOT assign pin locations (again, assuming we are using the X#Y# constraint method)? 

 

Thank you.

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roym
Moderator
Moderator
318 Views
Registered: ‎07-30-2007

These are the actual TX and RX pins.  They do not need location constraints because the GT wizard will located the GT_CHANNEL and that locates the TX and RX pins as well.  These are IO's so they must go to the top level.




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roym
Moderator
Moderator
319 Views
Registered: ‎07-30-2007

These are the actual TX and RX pins.  They do not need location constraints because the GT wizard will located the GT_CHANNEL and that locates the TX and RX pins as well.  These are IO's so they must go to the top level.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


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