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Observer
Observer
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Registered: ‎10-09-2018

[GTH]: RXRECCLKOUT connection 16 lane Tx and RX Protocol

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evaluation Board :ZCU104.

Purpose: test 16 lane TX and RX Protocol.

1. Is it Possible to connect RXRECCLKOUT to RX (as shown in the diagram)?

2. Is it possible TX and Rx in same FPGA and Test by Internal LoopBack (Near end) and External Loopback (with ac coupled) ?

3. For   GTH pin that has some direct connection ( say to HDMI ) in evaluation Board, will it possible to test our custom protocol (only internal Loopback) ?

GTH.jpg

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @pprajith89 

(1) I don't this clock connectivity possible.
You can connect RXRECLK output from one channel to OBUFDS_GTE3/4_ADV, but OBUFDS_GTE3/4 output cannot be connected to QPLL input directly. OBUFDS_GTE3/4 output will go to external pin.QPLL0 input should be feed from external MGTHREFCLK pins.
 
(2) Yes, this is a supported usecase

(3) I think this is possible.

Kind regards
Leo

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Xilinx Employee
Xilinx Employee
233 Views
Registered: ‎03-30-2016

Hello @pprajith89 

(1) I don't this clock connectivity possible.
You can connect RXRECLK output from one channel to OBUFDS_GTE3/4_ADV, but OBUFDS_GTE3/4 output cannot be connected to QPLL input directly. OBUFDS_GTE3/4 output will go to external pin.QPLL0 input should be feed from external MGTHREFCLK pins.
 
(2) Yes, this is a supported usecase

(3) I think this is possible.

Kind regards
Leo

View solution in original post

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Moderator
Moderator
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Registered: ‎07-30-2007

In addition for 1.  It would be possible to take the recovered clock off chip run it through a pll to clean the jitter and then use it as a reference clock but it could not be used to run the channel it is recovering the clock from.  You need a refclk to recover a clock but you need the recovered clock to generate the refclk.   There is a way, however, to use the recovered clock from the channel to modulate the fractional divider to modify the refclk frequency such that the TX is basically running off the recovered clock as the refclk.  See XAPP1276  https://www.xilinx.com/support/documentation/application_notes/xapp1276-vcxo.pdf 

 




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Observer
Observer
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Registered: ‎10-09-2018
thanks will check this document.