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Contributor
Contributor
514 Views
Registered: ‎07-25-2018

GTH Transceiver RX reset done toggling

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Hi,

i tried to implement  GTH transceiver(X0Y8) in ZCU102 board .I have obeserved that receiver reset done signal is toggling (gtwiz_reset_rx_done_out).

gtwiz_reset_rx_done_out changes from 1 to 0 data loss is occured on receiver side . I am sending my own data removed both PRBS Checker & generator module in example project.

To resolve gtwiz_reset_rx_done_out toggling problem . i have made rx_data_good_in always 1   in example_init_inst module . 

what is the reason for gtwiz_reset_rx_done_out  toggling ??

what shoulde be  input value  for rx_data_good_in  ??

Thanks & Regards

Pradeep

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Xilinx Employee
Xilinx Employee
467 Views
Registered: ‎11-29-2007

Re: GTH Transceiver RX reset done toggling

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hello

data_good is generally driven by the PRBS checker. If data are wrong a new reset will be asserted. This is just an implementation example in the GT Wizard, if you do not have incoming data, or your transmitter does not send PRBS data ... you will see periodic resets. This is expected.

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Newbie cc01
Newbie
485 Views
Registered: ‎02-11-2019

Re: GTH Transceiver RX reset done toggling

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As you said you have to put rx_data_good_in to always 1

there is a timer in the example design, and if timer expire and the rx_data_good is not 1, it will reset again trying to do the pattern gen and check again.

The way you change it is correct.

Xilinx Employee
Xilinx Employee
468 Views
Registered: ‎11-29-2007

Re: GTH Transceiver RX reset done toggling

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hello

data_good is generally driven by the PRBS checker. If data are wrong a new reset will be asserted. This is just an implementation example in the GT Wizard, if you do not have incoming data, or your transmitter does not send PRBS data ... you will see periodic resets. This is expected.

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Observer trafalgar
Observer
430 Views
Registered: ‎01-24-2019

回复: GTH Transceiver RX reset done toggling

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Hi,i am trying to implement GTH transceiver in ZCU102 board too. I have met some similar problems and have posted to community Forums for help but nobody replies for a long time. 

My problem is the GTH transceiver ip is always on the status of "reset",because“gtwiz_userclk_tx_reset_in” and “gtwiz_userclk_tx_reset_in” are always high.

This two signals in the example design are drivens by "rxpmaresetdone_out” and "txpmaresetdone_out" but this two signals are always "2'b00", so the transceivers is always reset.

I want to know how to let the transceiver finish the "reset" status and can work normally.

The simulation don't have this problem.

Thanks.

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Contributor
Contributor
421 Views
Registered: ‎07-25-2018

回复: GTH Transceiver RX reset done toggling

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Hi @trafalgar,

i want to know whether you are giving reset and free running clock to GTH Transceiver from ZCU102 board .

what are inputs  given to following signals in(_example_top.v):

input  ch0_gthrxn_in,
input ch0_gthrxp_in,
output  ch0_gthtxn_out,
output  ch0_gthtxp_out,
input hb_gtwiz_reset_clk_freerun_in,
input hb_gtwiz_reset_all_in,

which GTH channel you are using SFP or SMA(for Ex X0Y10)??

Pradeep

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Observer trafalgar
Observer
416 Views
Registered: ‎01-24-2019

回复: GTH Transceiver RX reset done toggling

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Hi,

Some details of my design can be seen in:

https://forums.xilinx.com/t5/Serial-Transceivers/Problems-of-zcu102-GTH-transceiver-on-board-achievement/m-p/934952 

Actually, input "ch0_gthrxn_in" and input "ch0_gthrxp_in" are connected to output "ch0_gthtxn_out" and output "ch0_gthtxp_out" in simulation.

The indata "gtwiz_userdata_tx_in" is from my design tx side and the outdata "gtwiz_userdata_rx_out" is to my design rx side.

Signals “hb_gtwiz_reset_clk_freerun_in” and "hb_gtwiz_reset_all_in" are given by myself in simulation.

In implementation, a zcu102's input "ch0_gthrxn_in" and input "ch0_gthrxp_in" are from another zuc102's output "ch0_gthtxn_out" and output "ch0_gthtxp_out" physically.

“hb_gtwiz_reset_clk_freerun_in”s source is USER_SI570. It's frequency is 300Mhz so I let it through the "clock wizard" ip to get the 250Mhz freerun_in clk.

"hb_gtwiz_reset_all_in" is from button and I have tested that it is effective.

GTH simulation is below:

simulation.png 

Simulation don't have problems.

The channel configuration is below:

3.png

The reference clock is from "USER_MGT_SI570". It is 156.25Mhz but the calculate value is 62.5 Mhz.

The only constraint is:

create_clock -name clk_mgtrefclk0_x0y2_p -period 16.0 [get_ports clk_in1_p1]

I guess the problem is here. It need 62.5Mhz ref clk but its source is 156.25Mhz.

I am trying to change the actual ref clk from 62.5Mhz to 156.25Mhz.

Deeply grateful,

Thanks.

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