UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor ldkazuma
Visitor
225 Views
Registered: ‎11-11-2019

GTH Transceiver Wizard: Instantiate both QPLL and CPLL

Jump to solution

I'm using a ZYNQ ultrascale+. My application requires me to dynamically switch between 10.4Ghz, 9.6Ghz, and 600Mhz line rates, using one 100Mhz reference clock.

Based on the diagram on UG576 pg 155, it looks like it should be possible to set up CPLL for the 600Mhz line rate and the QPLL for the other two, and then dynamically switch them with the async signal TXPLLCLKSEL. A similar thing would be possible on the receive side with RXPLLCLKSEL. This allows me to switch line rates without resetting any clocking logic (PLLs), just the GTHE4_CHANNEL Primitive.

However, I'm not too sure how to configure the GT wizard to do this. The GUI looks like it expects only one line rate on Tx and one line rate on Rx. The documentation says the wizard will autuomatically set up a CPLL Calibration block if CPLL clock resource is selected, and it will place down one Transceiver Common Primitive if QPLL0 or QPLL1 clock resource is selected. Is it possible to force the wizard to do both? 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎06-01-2017

Re: GTH Transceiver Wizard: Instantiate both QPLL and CPLL

Jump to solution

Hi @ldkazuma 

The general procedure for building a dynamic rate switching design is:

  1. Build xci for every targeted line rate. In your case, build 3 wizard IPs for 10.4, 9.6 and 0.6 Gbps (you mentioned Ghz but I assume you meant Gbps). Make sure the freerun clock is set at the correct targeted frequency for all generated xci's. The maximum allowed frequencies is lower for lower line rates (see PG182 Table 2-1).
  2. Open IP example design, run through implementation and open the implemented design
  3. Run the attached tcl script which will dump all attributes to an output file "gtParams.txt"
  4. Compare the attribute dumps and record all attributes that are different between rates. These will be the attributes that you will need to change through DRP at run time

In your real design:

  • Use the highest line rate as your base design for implementation which will close timing for the highest frequencies
  • Choose QPLL for your base design so that COMMON block is included
  • Set INCLUDE_CPLL_CAL = 1 so that the CPLL calibration block is forced to be included (see PG182 page 65)
  • For CPLL driven line rate(s), make sure the CPLL calibration block ports are driven correctly. See PG162 page 66, and also AR 70485

By the way, QPLL1 can run down to 500Mbps on Zynq US+ GTH. Potentially you can use QPLL1 on all 3 rates which will make your architecture simpler. You will only need to change attributes (through DRP) on the fly and not ports. Ports are not included in the attribute dump so extra care will need to be taken to get the design right.

In addition, I assume you are using TX/RX together and not independently. If not, check out issues when dynamically changing TXPLLCLKSEL/RXPLLCLKSEL described in AR 72254.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
146 Views
Registered: ‎06-01-2017

Re: GTH Transceiver Wizard: Instantiate both QPLL and CPLL

Jump to solution

Hi @ldkazuma 

The general procedure for building a dynamic rate switching design is:

  1. Build xci for every targeted line rate. In your case, build 3 wizard IPs for 10.4, 9.6 and 0.6 Gbps (you mentioned Ghz but I assume you meant Gbps). Make sure the freerun clock is set at the correct targeted frequency for all generated xci's. The maximum allowed frequencies is lower for lower line rates (see PG182 Table 2-1).
  2. Open IP example design, run through implementation and open the implemented design
  3. Run the attached tcl script which will dump all attributes to an output file "gtParams.txt"
  4. Compare the attribute dumps and record all attributes that are different between rates. These will be the attributes that you will need to change through DRP at run time

In your real design:

  • Use the highest line rate as your base design for implementation which will close timing for the highest frequencies
  • Choose QPLL for your base design so that COMMON block is included
  • Set INCLUDE_CPLL_CAL = 1 so that the CPLL calibration block is forced to be included (see PG182 page 65)
  • For CPLL driven line rate(s), make sure the CPLL calibration block ports are driven correctly. See PG162 page 66, and also AR 70485

By the way, QPLL1 can run down to 500Mbps on Zynq US+ GTH. Potentially you can use QPLL1 on all 3 rates which will make your architecture simpler. You will only need to change attributes (through DRP) on the fly and not ports. Ports are not included in the attribute dump so extra care will need to be taken to get the design right.

In addition, I assume you are using TX/RX together and not independently. If not, check out issues when dynamically changing TXPLLCLKSEL/RXPLLCLKSEL described in AR 72254.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post