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Adventurer
Adventurer
431 Views
Registered: ‎11-23-2018

GTH clock route issue

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Hello Everyone,

Design facing the issue in implementation upon changing the transceiver lane selection in physical resources tab og GT wizaed.

Attached is the current selection of physical resources of GTH. I followed UG917's page no. 40 for clock settings.

Quad 228:
• MGTREFCLK0 - FMC_HPC_GBTCLK0_M2C_C_P/N clock
• MGTREFCLK1 - FMC_HPC_GBTCLK1_M2C_C_P/N clock
• Contains four GTH transceivers allocated to FMC_HPC_DP[3:0]_C2M/M2C_P/N

I set MGTREFCLK1 with GTBTCLK1 comes from FMC. 

The design takes too much time in implementation & at the end, it gives delay violations. 

Can anyone guide me or correct me for GTH's setting of the lane?

gt_physical_resource.jpg
1 Solution

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Adventurer
Adventurer
277 Views
Registered: ‎11-23-2018

Re: GTH clock route issue

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With FPGA pin D2 D6, design successfully implemented. Without changing the timing constraints of the design.

View solution in original post

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Explorer
Explorer
402 Views
Registered: ‎03-16-2019

Re: GTH clock route issue

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your clock selection is what is said in ug917 (as you mentioned) and all things seem OK.

can you declare what is your application? and what is the schematic of your design?

tell us about your design timing constraints.

 

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Xilinx Employee
Xilinx Employee
378 Views
Registered: ‎11-29-2007

Re: GTH clock route issue

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hi

The choice of GT dedicated REFCLK route should not affect timing in fabric. 

Please check the timing report and see what is the real problem. Maybe the problem is due to the TX/RXUSRCLK frequency?

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Adventurer
Adventurer
345 Views
Registered: ‎11-23-2018

Re: GTH clock route issue

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Thanks, @gguasti for the quick response.

Please check the timing report and see what is the real problem. Maybe the problem is due to the TX/RXUSRCLK frequency?

I verified the timing report, constraints are given to take care of the timing-related path.

Meanwhile, With the same design I tried to implement with different settings of GT that is from one of my design.

Attached is a screenshot of GT configuration for which my design get successfully implemented.

I don't understand where the issue with previous settings.

gt_new_settings.jpg
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Adventurer
Adventurer
331 Views
Registered: ‎08-01-2017

Re: GTH clock route issue

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Hi,

Could you show us the violation net and route? Is it from type interpath or intrapath? 

Do you have any other constraint that changes with changing the design?


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Highlighted
Adventurer
Adventurer
278 Views
Registered: ‎11-23-2018

Re: GTH clock route issue

Jump to solution

With FPGA pin D2 D6, design successfully implemented. Without changing the timing constraints of the design.

View solution in original post

0 Kudos