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softwind555
Explorer
Explorer
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Registered: ‎05-14-2015

GTH line rate

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I'm using a "-1" speed Zynq Unltrascale+ device. In the datasheet DS925(V1.9) page 79, the link rate capability of GTH transceiver is listed as below. My question is: QPLL0 frequency range can reach up to 16.375gbps, why can't line rate go up to 16.375gbps? From the datasheet below, the line rate can go up to 12.5gbps only. 

LineRate.png

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borisq
Xilinx Employee
Xilinx Employee
1,931 Views
Registered: ‎08-07-2007

hi,

 

16 G is the max VCO frequency. it is the max clock source frequency.

the clock is driving the GT circuit.

 

however, due to timing limiation, the GT circuit cannot go that fast on -2 and -1.

 

that's why the clock source is not the bottom neck, but the GT circuit is.

 

thanks,

Boris

 

 

 

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borisq
Xilinx Employee
Xilinx Employee
1,932 Views
Registered: ‎08-07-2007

hi,

 

16 G is the max VCO frequency. it is the max clock source frequency.

the clock is driving the GT circuit.

 

however, due to timing limiation, the GT circuit cannot go that fast on -2 and -1.

 

that's why the clock source is not the bottom neck, but the GT circuit is.

 

thanks,

Boris

 

 

 

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softwind555
Explorer
Explorer
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Registered: ‎05-14-2015

Thank you! @borisq

I have another question. The datasheet says CPLL line rate range can go up to 8.5gbps. But, the page 7 of XAPP1248 says the line rate of CPLL for "-1" device can go up to only 4.25gbps. Why? 

LineRate.png

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borisq
Xilinx Employee
Xilinx Employee
1,462 Views
Registered: ‎08-07-2007

regarding line rate, pls follow ds892,

xapp is incorrect in regards to line rate range.

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