01-23-2020 07:30 AM
My GTH transceiver configuration is:
- Lane rate:10 Gbps
- User data interface width: 32-bit
- refclk frequency: 156.25 MHz
So the RXOUTCLK frequency must be 312.5 MHz (10G / 32).
For the Virtex 7 case, using the 7-series transceiver wizard I can select RXPLLREFCLK as clock source for the RXOUTCLK and the tool generate automatically an MCMM to generate the 312.5 MHz clock from the reference clock.
For the KU case, using the Ultrascale FPGAs tranceivers wizard (1.7) I can't select RXPLLREFCLK as a clock source for RXOUTCLK...
Why ? Can I do it in another way ?
I can select "RXPLLREFCLK DIV1 " only setting the refclk to 312.5 MHz but I don't want to do it because I only have a 156.25 MHz clock available in my design.
Thanks in advance for your help,
01-23-2020 08:38 AM - edited 01-23-2020 08:45 AM
The GT itself will generate a 312.5 from a 156.25 refclk is that is what the USRCLK needs to be. It will then use the divider in the BUFG_GT to do the /2 for the USERCLK2 (if a /2 is needed). The MMCM was needed to generate the /2 clock in the V7. Any of the three settings will give you a 312.5 based on the recovered clock and should work well for you.
Forcing the outclk to one of the refclk dividers won't give you a recovered clock and shouldn't be used unless the reference clock is synchronous to the reference clock on the far end. Further you shouldn't use an MMCM in UltraScale as it isn't needed and can deliver clocks that have too much skew between USRCLK and USRCLK2.
01-23-2020 08:44 AM
01-24-2020 12:00 AM
In my case, the refclk is synchronous to the reference clock of the transmitter on the far end.
I need a deterministic clock (compare to the far end clock used to provide data to the transmitter) in my design to compensate variable latency on the link through a FIFO and release data at a deterministic instant at the output of this same FIFO.
I was hopping to use the RXPLLREFCLK to generate my deterministic 312.5 MHz from the 156.25 MHz refclk.
Again, can I do that in another way in the FPGA?
Thank you for your support.
01-24-2020 07:45 AM
The GT will do that for you. It will set up the PLL and dividers to output an RXOUTCLK that is synchronous to the incoming data the same as a clock generated by an MMCM. The example design will be set up with exactly what you are looking for.
The RXBUFFER would seem to be the FIFO that you are looking for although you can drive the output of the GT into another fifo and create some slack if you wish.
You can use the ODIV2 output of the IBUFDS_GT* input buffer of the reference clock to drive an MMCM. Take the 312.5 output of the MMCM and drive it through a bufg_gt to USRCLK and another BUFG_GT with the /2 set to drive the USRCLK2. The 312.5 will be exactly equivalent to the RXOUTCLK from the example design and you would be wasting power and resources. You should use the RXOUTCLK as you would use the output of the MMCM you would like to create and have it drive whatever FIFO's and gates you need.