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Visitor
Visitor
695 Views
Registered: ‎07-04-2017

GTP RXOUTCLK frequency

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Hi,

I am facing the incorrect GTP RXOUTCLK frequency against expected in the silicon(XC7A35TFGG484-2).

I implemented both GTP Tx and Rx as following spec;

Datarate: 0.75Gbps

Data width: 20

Then, I connect between Tx and Rx port via SMA cable and start to transmitting the 8b10b coded data. However, the recovered data is wrong, and the RXOUTCLK frequency is 46.9MHz I confirmed. It is multiplied by 1.25 of expected(37.5MHz), so I guess the data width is set to 16 in GTP wrapper or somewhere, but I could not find such setting. And this design has been verified in the simulation with Xilinx AR #53561.
Please tell me how to solve this issue.

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Xilinx Employee
Xilinx Employee
656 Views
Registered: ‎10-19-2011

Hi @k_uno_sli ,

please check that you did not accidentally interrupted an ongoing reset.
You could verify if you read address 0x11 before you apply the reset and check the value
For bits [13:11] you should find a value of '3' or '5' there depending on your bus width.
If you see '2' or '4' there, you interrupted the reset before.

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Moderator
Moderator
665 Views
Registered: ‎07-30-2007

The external width of the bus will be divisible by 8 if you have 8B10B encoding.  The RXOUTCLK would be set up to drive a 16 wide bus.

On the TX side there is a 1.25 multiplier between the rate at the TXDATAIN and the TXP data.  For every 16 bits at TXDATAIN there are 20 bits at the TXP pin.  Could this be where the multiplier comes in?




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Xilinx Employee
Xilinx Employee
657 Views
Registered: ‎10-19-2011

Hi @k_uno_sli ,

please check that you did not accidentally interrupted an ongoing reset.
You could verify if you read address 0x11 before you apply the reset and check the value
For bits [13:11] you should find a value of '3' or '5' there depending on your bus width.
If you see '2' or '4' there, you interrupted the reset before.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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Visitor
Visitor
643 Views
Registered: ‎07-04-2017

Hi Roy,

Thank you for the reply.

In my design, the 8b10b encoder/decoder of GTP transceiver are not used, and I implemented another 8b10b encoder/decoder to outside of the GTP. So I set the external bus width to 20 in the transceiver wizard.

On the silicon, TXOUTCLK frequency is 1/20 * datarate (37.5MHz) and also correct symbols can be observed on the differential pins (MGTP_TX_P/N), however RXOUTCLK freuquency is multiplied by 1.25 against TXOUTCLK. Also on the simulation, both TXOUTCLK and RXOUTCLK frequency is 1/20 * datarate as expected.

Best Regards,

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Visitor
Visitor
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Registered: ‎07-04-2017

Hi ,

Thank you for your great support.

I had recheck and correct reset control logic of my design according to the advice.
I can observe correct Rx data and clock frequency from GTP now.

Best Regards,

 

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