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rkfournier
Adventurer
Adventurer
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Registered: ‎05-09-2018

GTP Simulation Speed-up

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I have a design that uses an Artix-7 device, and one GTP transceiver is dedicated to a PCIe implementation. Why does the PCIe simulation come fully functional after less than 100 microseconds of simulation time whereas the other GTPs require 1.3 milliseconds?

This makes it EXTREMELY painful to verify a new design. My simulation times exceed 12 hours on a Windows 7 platform that has a Windows Experience Index of 7.6.

Is there anyway that Xilinx can find a solution? We were spoiled by the Spartan-6 and it feels like a real step backwards moving to the Artix-7.

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rkfournier
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Registered: ‎05-09-2018

Turns out that I had changed from using Modelsim to the Vivado simulator, and Vivado was using the synthesis files for simulating the other three GTP transceivers. By changing over to the IP generated "*_sim_netlist.vhd" file in Vivado it solved both problems! The three transceivers are now ready within 50 microseconds from the start of the simulation.

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borisq
Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi @rkfournier

 

are you using 7 series Intergrated Block for PCI Express IP?

if so, you can select 'Enable PIPE Simulation' option.

It will be much faster.

 

Thanks,

Boris

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rkfournier
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Registered: ‎05-09-2018

Hi Boris,

   The PCIe is not the issue, it is the other three GTP transceivers in my design.  All are from the same quad. The gt_txresetdone is completed in 67 microseconds, while the gt_rxresetdone is still not completed even after 1.6 milliseconds of simulation time. What can I do to speed-up the other three GTPs? What is the PCIe doing that I can replicated for the other three transceivers?

 

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rkfournier
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Registered: ‎05-09-2018

Something seems to be wrong with the IP for the other three GTP transceivers. The RXPMARESETDONE is going to an undefined state shortly after the start of simulation. The GTPs are also not generating RX clocks.

I am currently investigating this new issue. 

rkfournier
Adventurer
Adventurer
1,276 Views
Registered: ‎05-09-2018

Turns out that I had changed from using Modelsim to the Vivado simulator, and Vivado was using the synthesis files for simulating the other three GTP transceivers. By changing over to the IP generated "*_sim_netlist.vhd" file in Vivado it solved both problems! The three transceivers are now ready within 50 microseconds from the start of the simulation.

View solution in original post