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Participant
Participant
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Registered: ‎02-08-2019

GTP Transceiver TXOUTCLK Driving

Hello 

I found following at page 81 of  the user guide for 4 byte mode. The TXUSRCLK/TXUSRCLK2 is driving by TXOUTCLK.

My question is

In this mode MMCME2 is instantiated by application code or it is instantiated by itself and no need to do in application code?

GTP_4_BYTE.JPG

Thanks

Manish

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Xilinx Employee
Xilinx Employee
265 Views
Registered: ‎03-30-2016

Re: GTP Transceiver TXOUTCLK Driving

Hello Manish@manb 

GTP user is responsible to supply TXUSRCLK/TXUSRCLK2.
so if you are using GTP Transceiver wizard, the wizard will not instatiate MMCM inside the IP,
But you can generate Example Design for your reference (which include an MMCM)

Regards
Leo

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Adventurer
Adventurer
244 Views
Registered: ‎05-07-2018

Re: GTP Transceiver TXOUTCLK Driving

hi

This is MMCM that generate Txusrclk/Txusrclk2 in GT

I made some changes because of my design.

You can find that in example design with gt_usrclk_source.

Good luck

 


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

--***********************************Entity Declaration*******************************
entity GBT_GT_USRCLK_SOURCE is
port
(

GT0_TXUSRCLK_OUT : out std_logic;
GT0_TXUSRCLK2_OUT : out std_logic;
GT0_TXUSRCLK8_OUT : out std_logic;
GT0_TXOUTCLK_IN : in std_logic;
GT0_TXCLK_LOCK_OUT : out std_logic;
GT0_TX_MMCM_RESET_IN : in std_logic;
GT0_RXUSRCLK_OUT : out std_logic;
GT0_RXUSRCLK2_OUT : out std_logic;
GT0_RXUSRCLK8_OUT : out std_logic;
GT0_RXOUTCLK_IN : in std_logic;
GT0_RXCLK_LOCK_OUT : out std_logic;
GT0_RX_MMCM_RESET_IN : in std_logic;
Q1_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
Q1_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
Q1_CLK0_GTREFCLK_OUT : out std_logic
);


end GBT_GT_USRCLK_SOURCE;

architecture RTL of GBT_GT_USRCLK_SOURCE is

component GBT_CLOCK_MODULE is
generic
(
MULT : real := 2.0;
DIVIDE : integer := 2;
CLK_PERIOD : real := 6.4;
OUT0_DIVIDE : real := 2.0;
OUT1_DIVIDE : integer := 2;
OUT2_DIVIDE : integer := 2;
OUT3_DIVIDE : integer := 2
);
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic;
-- Status and control signals
MMCM_RESET_IN : in std_logic;
MMCM_LOCKED_OUT : out std_logic
);
end component;

--*********************************Wire Declarations**********************************

signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;

signal gt0_txoutclk_i : std_logic;
signal gt0_rxoutclk_i : std_logic;

attribute syn_noclockbuf : boolean;
signal q1_clk0_gtrefclk : std_logic;
attribute syn_noclockbuf of q1_clk0_gtrefclk : signal is true;

signal gt0_txusrclk_i : std_logic;
signal gt0_txusrclk2_i : std_logic;
signal gt0_txusrclk8_i : std_logic;
signal gt0_rxusrclk_i : std_logic;
signal gt0_rxusrclk2_i : std_logic;
signal gt0_rxusrclk8_i : std_logic;
signal txoutclk_mmcm0_locked_i : std_logic;
signal txoutclk_mmcm0_reset_i : std_logic;
signal gt0_txoutclk_to_mmcm_i : std_logic;
signal rxoutclk_mmcm1_locked_i : std_logic;
signal rxoutclk_mmcm1_reset_i : std_logic;
signal gt0_rxoutclk_to_mmcm_i : std_logic;


begin

--*********************************** Beginning of Code *******************************

-- Static signal Assigments
tied_to_ground_i <= '0';
tied_to_vcc_i <= '1';
gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;

Q1_CLK0_GTREFCLK_OUT <= q1_clk0_gtrefclk;

--IBUFDS_GTE2
ibufds_instq1_clk0 : IBUFDS_GTE2
port map
(
O => q1_clk0_gtrefclk,
ODIV2 => open,
CEB => tied_to_ground_i,
I => Q1_CLK0_GTREFCLK_PAD_P_IN,
IB => Q1_CLK0_GTREFCLK_PAD_N_IN
);



-- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
-- for improved jitter performance, and to avoid consuming an additional BUFG
txoutclk_mmcm0_reset_i <= GT0_TX_MMCM_RESET_IN;
txoutclk_mmcm0_i : GBT_CLOCK_MODULE
generic map
(
MULT => 4.0,
DIVIDE => 1,
CLK_PERIOD => 6.25,
OUT0_DIVIDE => 4.0,
OUT1_DIVIDE => 2,
OUT2_DIVIDE => 16,
OUT3_DIVIDE => 1
)
port map
(
CLK0_OUT => gt0_txusrclk2_i,
CLK1_OUT => gt0_txusrclk_i,
CLK2_OUT => gt0_txusrclk8_i,
CLK3_OUT => open,
CLK_IN => gt0_txoutclk_i,
MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
MMCM_RESET_IN => txoutclk_mmcm0_reset_i
);


rxoutclk_mmcm1_reset_i <= GT0_RX_MMCM_RESET_IN;
rxoutclk_mmcm1_i : GBT_CLOCK_MODULE
generic map
(
MULT => 2.0,
DIVIDE => 1,
CLK_PERIOD => 3.125,
OUT0_DIVIDE => 4.0,
OUT1_DIVIDE => 2,
OUT2_DIVIDE => 16,
OUT3_DIVIDE => 1
)
port map
(
CLK0_OUT => gt0_rxusrclk2_i,
CLK1_OUT => gt0_rxusrclk_i,
CLK2_OUT => gt0_rxusrclk8_i,
CLK3_OUT => open,
CLK_IN => gt0_rxoutclk_i,
MMCM_LOCKED_OUT => rxoutclk_mmcm1_locked_i,
MMCM_RESET_IN => rxoutclk_mmcm1_reset_i
);

 


GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
GT0_TXUSRCLK8_OUT <= gt0_txusrclk8_i; --gt0_rxusrclk8_i; --gt0_txusrclk8_i;
GT0_TXCLK_LOCK_OUT <= txoutclk_mmcm0_locked_i;
GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
GT0_RXUSRCLK8_OUT <= gt0_rxusrclk8_i;
GT0_RXCLK_LOCK_OUT <= rxoutclk_mmcm1_locked_i;
end RTL;

GT.PNG