07-12-2019 10:44 AM
It would be very convenient to provide only one high quality clock to my FPGA. In the example I generated I have the Q0_CLK0_GTREFCLK_PAD input pins fed by a crystal oscillator. When I try to feed Q0_CLK0_GTREFCLK_OUT from gtwizard_0_GT_USRCLK_SOURCE back to sysclk_in in gtwizard_0_support the compiler complains, saying that the clocks cannot be from the same source. The apparent violation is found in UG482 page 36 for the PLL#LOCKDETCLK signals: "Stable reference clock for the detection of the feedback and reference clock signals to the PLL. The input reference clock to the PLL or any output clock generated from the PLL (e.g., TXOUTCLK) must not be used to drive this clock. This clock is required only when using the PLL[0/1]FBCLKLOST and PLL[0/1]REFCLKLOST ports. It does not affect the PLL lock detection, reset, and power-down functions." Is there a good way around this? I have managed to trick the FPGA by routing Q0_CLK0_GTREFCLK_OUT to an output pin, connecting it to an input pin, and then using it for my system and DRP clocks. It works on real hardware, but the full ramifications of doing so are beyond my feeble understanding.
07-15-2019 06:59 AM - edited 07-15-2019 07:12 AM
In order to use the LOCKDETCLK you need to have 2 clock inputs. You could run the ODIV2 output clock from the IBUFDS_GTE* through a BUFG and use that to drive the LOCKDETCLK. This is a free running clock and should meet the requirements and not trigger an error message except that you are using the refclk input to detect the loss of the refclk input. That defeats the purpose. If the refclk input is an output of a normal oscillator it may be safe to assume it will be running. If PLL's and switches are involved in generating the refclk you may need to make allowances for a new clock input. It doesn't have to be very high quality like the reference clock but it needs to be reliable.