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sa_fpga
Observer
Observer
740 Views
Registered: ‎11-11-2019

Dear Xilinx Community,

I actually tried to post a question in area for "Serial Transceivers", but I get a "read only" message. Can somenone please with the right permissions move this post to the correct area?

So here comes my actual question:

I used vivado 2019.1.3 and 7 series FPGAs Transceivers Wizard (3.6) to genarate a GTP 3G-SDI Receiver (TX part disabled) for an Artix-7 device. 

I use a https://shop.trenz-electronic.de/en/TE0714-03-35-2I-FPGA-Module-with-Xilinx-Artix-7-XC7A35T-2CSG325I-3-3-V-Configuration-4-x-3-cm board an ILA to test the desing. The GTP seem to be running. GT0_RX_FSM_RESET_DONE_OUT goes high and GT0_RXUSRCLK2_OUT is generated. My problem is that data on the GT0_RXDATA_OUT seems to be a random noise with a 8-times higher data rate than expected. See the screenshot from ILA. As the source for the GTP I use an HDMI to 3G-SDI Converter. The output on GT0_RXDATA_OUT stays random also if I disconnect the source and even if I pull it high or low. In the simulation it seems to work.

Thanks in advance for any hint in right direction.

 

 

 

 

rxdata_out.png
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eschidl
Xilinx Employee
Xilinx Employee
633 Views
Registered: ‎10-19-2011

Hi @sa_fpga ,

let me raise the question the other way around.
If the RXUSRCLK you show there is 148.5MHz and is real, the sampling clock of the ILA is running at 20 times that.

The maximum BUFG frequency according to datasheet in an Artix-7 -3 device is 680MHz.

How do you clock your ILA?

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drjohnsmith
Teacher
Teacher
719 Views
Registered: ‎07-09-2009
cant see much there
You say your using ILA, so I assume this is not a simulation,

some pointers
https://www.xilinx.com/Attachment/Hardware_Debug_Best_Practices.pdf

https://www.xilinx.com/support/documentation/application_notes/xapp1322-transceiver-link-tuning.pdf
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sa_fpga
Observer
Observer
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Registered: ‎11-11-2019

Hello drjohnsmith,

 

thank you for the link to the GT Debugger. I will try to use it. 

No this is not a simulation. The screenshot is from ILA running on the XC7A35T device. I really cannot understand why the data on GTP output has a data rate of 8-times the GT0_RX_USRCLK2_OUT. 

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sa_fpga
Observer
Observer
700 Views
Registered: ‎11-11-2019

I have to correct myself, the GTP output data rate is 20-times the GT0_RX_USRCLK2_OUT. I only counted the high side of the GT0_RX_USRCLK2_OUT and by mistake counted up till 8 not 10. 20 times the GT0_RX_USRCLK2_OUT (148,5 MHz for 3G-SDI) makes 2,976G. This is exactly the line rate of the GTP input. So why doI see the input line rate on the GTPs output?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009
Without the code, not much more we can do
have you been through the documents above and the debuging highlighted in there ?
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sa_fpga
Observer
Observer
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Registered: ‎11-11-2019

I will tidy up my project and write some comments before uploading it tommorow in the morning. Parallel I am ckecking the debugging app notes. Thanks!

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eschidl
Xilinx Employee
Xilinx Employee
634 Views
Registered: ‎10-19-2011

Hi @sa_fpga ,

let me raise the question the other way around.
If the RXUSRCLK you show there is 148.5MHz and is real, the sampling clock of the ILA is running at 20 times that.

The maximum BUFG frequency according to datasheet in an Artix-7 -3 device is 680MHz.

How do you clock your ILA?

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sa_fpga
Observer
Observer
536 Views
Registered: ‎11-11-2019

Hello Eschidl,

that's exactly what I am wondering! ILA is clocked by the 25 MHzsystem clock. I routed the GT0_RX_USRCLK2_OUT to an output pin and checked it with oscilloscope/spectrum analyzer. It's exactly 148.5 MHz, so it's real. 

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sa_fpga
Observer
Observer
514 Views
Registered: ‎11-11-2019

Hello,

thank you for the hint with the ILAc clock frequency. I changed it to 148.5MHz and now it works and the data showed by ILA makes sence. Thank you all for the help.

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drjohnsmith
Teacher
Teacher
499 Views
Registered: ‎07-09-2009
@eschide , well spotted
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