10-18-2019 10:39 AM
I am running into a case where occasionally on powerup none of my CPLLs are locking (CPLLLOCK=0). Sometimes the CPLLFBCLKLOST powers up asserted as well. When this unlocked state occurs at powerup I am unable to obtain a lock by any means including the following.
1. Power cycle CPLL using CPLLPD and then trigger reset to example design STARTUP_FSMs.
2. Disable then enable input refclk clock part on PCB, then trigger reset to example design STARTUP_FSMs.
I know all my signals are connected correctly because when it does powerup cleanly I am able to force an unlock by either powering down the CPLL or disabling the refclk input oscillator. When the CPLL powers up in a locked state everything works great and nothing I do to the CPLL pushes it into the unrecoverable unlocked state I see randomly at powerup. The only fix for this issue at the moment is continuously power cycle until the CPLL comes up in a locked state. Please advise!
10-18-2019 04:06 PM
In my point of view, This issue is because of your board designing and not related to the Gth transciver.
Could you post schematic of the board?
Did your board pass all xilinx recommandation for pcb designing?
10-21-2019 05:19 AM
I would like to avoid posting the schematic and you provide a fair assessment but I am following all of the PCB design requirements for the GTX transceivers. I also referenced the KC705 example design and included the additional bypassing it used in my design beyond the recommended components. The external 125Mhz reference clock input is well within the specification outlined in DS182 pages 58-59. It passes through 1:2 fanout buffer so I am able to clock 4 GTX quads from the same clock source (MGT_114 through MGT_117). The 2 driven clocks enter MGTREFCLK0_114 and MGTREFCLK0_116 which are shared with MGT_115 and MGT_117 respectively. Clock is AC coupled and routed on 100ohm impedance controlled traces.
Following configuration when I witness an unlocked state I try to power down the CPLL then perform a full SOFTRESET which includes the CPLLRST and it does not recover. This is the part that is baffling to me because regardless of possible incorrect delays at startup and sequencing conditions how does the CPLL get in an UNRECOVERABLE STATE? Please note that all 16 of the CPLLs seem to fail simultaneously meaning they all lock at powerup or none of then lock at powerup.
10-21-2019 06:09 AM
could you find out that when your CPLL loss, does your mgt clock has a valid clock ( by using oscilloscope)?
10-21-2019 07:56 AM
What type of configuration programming do you use? Does programming using the jtag cable (slower programming) work more often? Is it only on power up that you have the problem?
10-21-2019 09:06 AM
Master x16 BPI programming. Its only on powerup that I have seen this persistent unlocked state. I haven't been able to reproduce this issue programming directly over JTAG. I did check "Extend the reset to 3ms" in the GTX wizard but it doesn't change anything in the lower level generated files. It appears that the extended reset is now hardcoded in the 2018.3 generated files regardless of the checkbox state. Ignoring the correct delays and faster BPI programming time why wouldn't a cpllreset recover the CPLL well after the part has been programmed?
10-21-2019 09:14 AM - edited 10-21-2019 09:18 AM
A power spike can cause problems that you won't recover from easily. Somehow I believe your causing problems described in http://www.xilinx.com/support/answers/59294.htm Make sure the CPLL is held in power down until after configuration is complete and the reference clock is present. You must have done something to undo the normal set up of the CPLLPD pin.
10-22-2019 04:01 AM
Gaining oscilloscope access to the board during operation is challenging but it is possible. I designed in a counter driven by RXOUTCLKFABRIC which taps the REFCLK before entering the CPLL and it appears that this clocks input flatlines in my unlocked state. Therefore this points to the input 125MHz oscillator (DSC1103) ocassionally not oscillating at powerup or the 1:2 fanout buffer (SY58606) not passing the clock input to outputs. Both parts have good byapssed power and are well within their operating temperature ranges when this phenomenom occurs so I will have to get probes on these parts to discover which one is the offender.
10-22-2019 08:20 AM
During power up and just after configuration the AC coupling cap on the refclk has to charge to the right voltage before the signal will be seen internally. Could this be the issue? You just need to make sure the CPLLPD is set high when there is no input. One way this can be handled if this is a new design is to switch the .1uF ac coupling cap to a .01uf cap that is recommended for new designs.