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Visitor camber
Visitor
175 Views
Registered: ‎02-01-2019

GTX Clocking

I have an issue in placing a design which uses two transceivers configured as single lane Interlaken links, in that I get a placement error during the implementation phase of a build (see attached document). I am using transceivers from the second Quad in the device and heve defined the reference clock as one of the two clock inputs to that quad (clock is GTP_CLK_C_P and _N in the schematic snippet in the attached document). In the pin .xdc file the clock input is located at the required pins as are the Tx and Rx pairs. I am using the CPLLs in the transceiver block as the QPLL is not in the available PLL sources  for this device (xc7k160tfbg676) when I use the transceiver wizard to configure the transceiver. I generate an example design using the wizard and in the attached generated  ikln_1_a_support.vhd  file the common0_i module is instantiated. This module seems to be referencing the QPLL only so I am unsure why it is there.

I should add that the top-level design only requires one transceiver to be used. The system will consist of two boards with different geographic locations and the transceiver used will depend on that location.

Any pointers to where to unscamble this issue would be gratefully received.

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2 Replies
Moderator
Moderator
170 Views
Registered: ‎07-30-2007

Re: GTX Clocking

Each of your designs will instantiate a GT*_COMMON and since they are place in the same quad both will try to be placed in the same position which will cause a collision.  Even though you don't use the QPLL the common is placed so that the bias_cfg attribute can be instantiated.  You need to remove the common from one of the designs.  There is also a potential collision on the IBUFDS_GTE2 refclk buffer.  You may need to remove this buffer from one design and drive its outputs from the buffer in the other design.  In most IP the IBUFDS_GTE will be in the top level so it shouldn't be too difficult.




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Visitor camber
Visitor
160 Views
Registered: ‎02-01-2019

Re: GTX Clocking

Hi

Thanks for the quick response. I am iomplementing the clock buffer at the top level and feeding the output to the two CPLLs. I will do as you suggets in hand crafting one of the generated modules to remove the common module at that level.

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