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Newbie
Newbie
196 Views
Registered: ‎01-02-2019

GTX TRANSCEIVERS RX Problems

GTX TRANSCEIVERS

Hi people,

I am trying to use the GTX Transceivers in the ZCU106. Currently I have instantiated a GTX IP Core using the wizard. Furthermore, we have designed two extra modules to wrap the TX and RX signals.

We need use this GTX, to design a “BERometer” like a System BER, but we need to use our company HMI software, it is mandatory.

My design is approximately this:

Link_checker (top)
RX_Wrapper (to control GTX RX signals).
PRBS (designed manually).
TX_Wrapper. (to control GTX TX signals).
PRBS (designed manually).
GTX_Transceiver_IP_core.

Basic Configuration (Basic_configuration.png)


The problem is that the data received from RX is not the same that we are sending but is similar.

For example, we transmit 00_00_00_AA, but we receive 00_00_00_55, that is, the same minus the last 0.

We are using the following method to transmit the data. When TX counter (txsequence) is 32 or 0, we write the word in data line. ¿Is this correct?

(TX.png)

The RX wrapper only read the value from rx data out when rxdatavalid_out is 0 (I think…), but you can see that the RX is wrong. The correct word must be 00_00_00_AA.

(RX.png)

Any advice to solve my problem?

If you need more information, please let me know and we will provide it.

The documents that I have checked are:

UltraScale ArchitectureGTH Transceivers
UltraScale FPGAs Transceivers Wizard v1.7

Tags (1)
RX.png
Basic_Configuration.png
TX.png
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5 Replies
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Xilinx Employee
Xilinx Employee
184 Views
Registered: ‎03-30-2016

Hello @rlozanot 

Why did you set TXHEADER as a constant 2'b00 ?
You need to set TXHEADER[1:0] correctly to send 64B66B payload correctly.
TXHEADER=2'b00 is an invalid header value.

Regards
Leo

Highlighted
Newbie
Newbie
169 Views
Registered: ‎01-02-2019

Hi Leo,

First of all, thank you for the reply.

I have changed the value for header to 2'b01, but the problem still persist. Are 2'b01 a wrong value? Where can I search de correct values for header, any document?

Thank you in advance,

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Xilinx Employee
Xilinx Employee
155 Views
Registered: ‎03-30-2016

Hello @rlozanot 


>Are 2'b01 a wrong value? Where can I search de correct values for header, any document?

 

You need to set TXHEADER=2’b01 for data payload and TXHEADER=2’b10 for data+control character payload.

Anyway, You might need to understand the 64B/66B encoding scheme first, before start doing simulation.

64B66B encoding/decoding scheme is not the property of Xilinx, so Xilinx document does not cover details of 64B66B encoding/decoding scheme.

Sorry, Please try to search for 64B66B document online instead.

 

One more important tip.
You need to scramble your payload data to use 64B66B encoding.

 

Thanks
Leo

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Xilinx Employee
Xilinx Employee
149 Views
Registered: ‎03-30-2016

Hi,

 

Done some search. I just found a good doc on this topic:

http://www.ieee802.org/3/bn/public/mar13/hajduczenia_3bn_04_0313.pdf

 

Hope this helps.

 

Thanks
Leo

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Newbie
Newbie
145 Views
Registered: ‎01-02-2019

Hi!

Thank so much for the reply. I will read more documentation about the encoding scheme.

Kind Regards,

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