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Dasarath
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Visitor
310 Views
Registered: ‎03-30-2021

GTX data rates

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Hi,

I am working on parallel to serial conversion using GTX.

The FPGA is xc7v2000tflg1925-1.

When I configure the GTX Data Rate 4.4 Gbps and Reference clock as 110Mhz.

It works in simulations and also on board.

But when I configure the GTX Data Rate as 4.44 Gbps and Reference clock as 111.1Mhz.

In simulation the TX serial lines are not toggling ( for cadence environment but works with vivado simulation).

But on board, there is no CPLL lock is asserted, .i.e the output clocks are not coming from GTX

GTX reference clock and reset are properly applied.

Please help me to resolve the issue.

 

Thanking you,

 

Regards

P Dasarath

 

 

 

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roym
Moderator
Moderator
251 Views
Registered: ‎07-30-2007

It would have to be 4.444  for the refclk to be 111.1 Mhz.  Are you using comma alignment?  If so monitor byteisaligned and byterealign.  You need to have rxslide turned off unless your using it.




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roym
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Moderator
252 Views
Registered: ‎07-30-2007

It would have to be 4.444  for the refclk to be 111.1 Mhz.  Are you using comma alignment?  If so monitor byteisaligned and byterealign.  You need to have rxslide turned off unless your using it.




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drjohnsmith
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Teacher
233 Views
Registered: ‎07-09-2009

One question, why you looking at such an unusual frequency of 111,1 MHz,

     can you easily get a clock oscillator for that frequency ?

 

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Dasarath
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Registered: ‎03-30-2021

I am working on parallel to serial and serial to parallel .i.e chip to chip data transmission.

The data comes at 55.55Mhz, so I chose that data rate.

 

Thanks for your support.

The GTX issue got resolved. It's issue with on board clock.

Once we rectify it, GTX are working.

 

Thanks again.

 

Regards

P Dasarath

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drjohnsmith
Teacher
Teacher
171 Views
Registered: ‎07-09-2009

Ok,

 

A note, 

   you will be using a protocol on the link such as Aurora to ensure synchronisation , status info and lock ?

       These are packet based, 

thus the data rate on the channel has no link to the link clock rate, 

   data rate could be dc up to max, the protocol takes care of the rest.

 

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