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Adventurer
Adventurer
805 Views
Registered: ‎08-15-2018

GTY - BUFG_GT_SYNC

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Using a GTY - I switched the QPLL usage to a CPLL. I get this error in implementation:

 

[Place 30-754] Unroutable Placement! A BUFG_GT_SYNC and its driver are not placed in a routable site pair. The pair needs to be placed into specific sites in the same clock region in order to use the dedicated path between them.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

 

The interface is the same - the RXOUTCLK is driving the fabric and the USRCLK pins. Why would this error occur?

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Xilinx Employee
Xilinx Employee
767 Views
Registered: ‎06-01-2017

Check to see if all BUFG_GT have the same control signals for CE and CLR.

The CPLL calibration logic will add one more BUFG_GT. It's probably that this new BUFG_GT does not have the same CE and CLR as your existing ones. If so, the wizard will insert an independent BUFG_GT_SYNC. When you have too many BUFG_GT_SYNC, it cannot fit in the same clock region, and thus the error.

Modify your existing BUFG_GT's CE/CLR pins to match the CPLL BUFG_GT CE/CLR.

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Xilinx Employee
Xilinx Employee
787 Views
Registered: ‎06-01-2017

When you refer to "switched the QPLL usage to a CPLL", did you regenerate the xci? Or how did you make the change?

The placement error likely comes from wrong clock connections. 

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Adventurer
Adventurer
781 Views
Registered: ‎08-15-2018

I regenerated the output products if that’s what you mean.

the reference clock comes into refclk and goes out RXCLKOUT. They are the same for QPLL or CPLL. I didn’t change any ports.

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Xilinx Employee
Xilinx Employee
777 Views
Registered: ‎06-01-2017
The QPLL needs the COMMON but CPLL does not. If you had the COMMON outside of the core then regenerating output products would not remove the COMMON, but connections may not be right. In the last tab of the wizard GUI chooses whether COMMON is in the core or in the example design. Also, if you have any other block placed in the example design, those will not be updated with regenerating output products. Try open in example design again.
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Adventurer
Adventurer
776 Views
Registered: ‎08-15-2018

I removed common - the error is in implementation. Synthesis passes fine - so xci ports isn’t an issue.

my question is the same - how can the clock routing be wrong if the clock paths did not change?

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Xilinx Employee
Xilinx Employee
768 Views
Registered: ‎06-01-2017

Check to see if all BUFG_GT have the same control signals for CE and CLR.

The CPLL calibration logic will add one more BUFG_GT. It's probably that this new BUFG_GT does not have the same CE and CLR as your existing ones. If so, the wizard will insert an independent BUFG_GT_SYNC. When you have too many BUFG_GT_SYNC, it cannot fit in the same clock region, and thus the error.

Modify your existing BUFG_GT's CE/CLR pins to match the CPLL BUFG_GT CE/CLR.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post